• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.3
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• pp.224-230
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• 2016

In this study, a single-power-conversion series-resonant ac-dc converter with high efficiency and high power factor is proposed. The proposed ac-dc converter consists of single-ended primary-inductor converter with an active-clamp circuit and a voltage doubler with series-resonant circuit. The active-clamp circuit clamps the surge voltage and provides zero-voltage switching of the main switch. The series-resonant circuit consists of leakage inductance $L_{lk}$ of the transformer and resonant capacitors $ C_{r1}$ and $ C_{r2}$. This circuit also provides zero-current switching of output diodes $D_1$ and $D_2$. Thus, the switching loss of switches and reverse-recovery loss of output diodes are considerably reduced. The proposed ac-dc converter also achieves high power factor using the proposed control algorithm without the addition of a power factor correction circuit and a dc-link electrolytic capacitor. A detailed theoretical analysis and the experimental results for a 1kW prototype are discussed.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.393-398
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• 2014

A highly efficient dual-mode linear CMOS stacked-FET power amplifier (PA) is implemented for 3G UMTS and 4G LTE handset applications. High efficiency is achieved at a backed-off output power ($P_{out}$) below 12 dBm by employing an active-bypass amplifier, which consumes very low quiescent current and has high load-impedance. The output paths between high- and low-power modes of the PA are effectively isolated by using a bypass switch, thus no RF performance degradation occurs at high-power mode operation. The fabricated 900 MHz CMOS PA using a silicon-on-insulator (SOI) CMOS process operates with an idle current of 5.5 mA and shows power-added efficiency (PAE) of 20.5%/43.5% at $P_{out}$ = 12.4 / 28.2 dBm while maintaining an adjacent channel leakage ratio (ACLR) better than -39 dBc, using the 3GPP uplink W-CDMA signal. The PA also exhibits PAE of 35.1% and $ACLR_{E-UTRA}$ of -33 dBc at $P_{out}$ = 26.5 dBm, using the 20 MHz bandwidth 16-QAM LTE signal.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.3B no.3
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• pp.147-154
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• 2003

This paper presents a high-frequency boost type ZVS-PWM chopper-fed DC-DC power converter with a single active auxiliary edge-resonant snubber at the load stage which can be designed for power conditioners such as solar photovoltaic generation, fuel cell generation, battery and super capacitor energy storages. Its principle operation in steady-state is described in addition to a prototype setup. The experimental results of boost type ZVS-PWM chopper proposed here, are evaluated and verified with a practical design model in terms of its switching voltage and current waveforms, the switching v-i trajectory and the temperature performance of IGBT module, the actual power conversion efficiency, and the EMI of radiated and conducted emissions, and then discussed and compared with the hard switching scheme from an experimental point of view. Finally, this paper proposes a practical method to suppress parasitic oscillation due to the active auxiliary resonant switch at ZCS turn-off mode transition with the aid of an additional lossless clamping diode loop, and can be reduced the EMI conducted emission.

• Journal of Korea Port Economic Association
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• v.31 no.4
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• pp.121-132
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• 2015

Yangsan ICD (Inland Container Depot) has played an important role for Busan Port and Korea's port & logistics industries, increasing international logistics competitiveness and containers' transportation competitiveness in Busan region dealing with 1330 thousand TEU in 2005, since its opening in March 2000. However, it is necessary to seek new measures to revitalize Yangsan ICD, since its cargo volume decreased rapidly owing to the opening of Busan New Port and hinterland in 2006. This study constructed an evaluation model using AHP (Analytic Hierarchy Process) and conducted a survey targeting local businesses and persons concerned in Yangsan ICD to seek measures for revitalization. The results suggest that Yangsan ICD needs to switch functions to logistics centers (terminal facilities, logistics warehouse) for revitalization considering its advantage of facility location. Moreover, by extending the utilization period and securing building-to-land ratio, existing and new businesses' stable activity should be guaranteed. Furthermore, utilizing facilities such as the railway station in ICD, an active railway revitalization policy may increase cargo volume. Yangsan ICD should perform its role as an inland logistics depot through the revitalization of railway freight transportation in the national logistics system focusing on road freight transportation.

• The Journal of the Korea Contents Association
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• v.5 no.3
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• pp.217-225
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• 2005

Currently the research on input-queued ATM switches is one of the most active research fields. Many achievements have been made in the research on scheduling algorithms for input-queued ATM switches and also applied in commerce. The scheduling algorithms have the characteristics of improving throughput, satisfying QoS requirements and providing service fairly. In this paper, we studied on an implementation of scheduler which arbitrates the input-queued ATM switches efficiently and swiftly. The proposed scheduler approximately provides $100\%$ throughput for scheduling. The proposed algorithm completes the arbitration for N-port VOQ switch with 4-iterative matching. Also the proposed algorithm has a merit for implementing the scheduling algorithm with 1/2 area compared to that of iSLIP scheduling algorithm which is widely used. The performance of the proposed scheduling algorithm is superior to that of iSLIP in 4-iterative matching.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.21-26
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• 2005

An area efficient, low power switch-matrix semidigital FIR reconstruction filter for delta-sigma D/A converter is proposed. Filter coefficients are quantified to 7-bit and 7 current sources that correspond to each coefficient bit are used. The proposed semidigital FIR reconstruction filter is designed in a 0.25 um CMOS process and incorporates 1.5 mm$^{2}$ of active area and a power consumption is 3.8 mW at 2.5 V supply. The number of switching transistors is 1419 at 205 filter order. Simulation results show that the filter output has a dynamic range of 104 dB and 84 dB attenuation of out-of-band quantization noise.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.685-691
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• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, considering linearity, power consumption, chip area, and glitch energy. The low-glitch switch driving circuit is employed to improve the linearity and the dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core. The prototype DAC is implemented in a 0.35 urn n-well single-poly quad-metal CMOS technology. The measured DNL and INL of the prototype DAC are within $\pm$0.75 LSB and $\pm$1.73 LSB, respectively, and the spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of 2.2 mm ${\times}$ 2.0 mm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.4
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• pp.629-637
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• 2006

Currently the research on input-queued ATM switches is one of the most active research fields. Many achievements have been made in the research on scheduling algorithms for input-queued ATM switches and also applied in commerce. The scheduling algorithms have the characteristics of improving throughput, satisfying QoS requirements and providing service fairly. In this paper, we studied on an implementation of scheduler which arbirates the input-queued ATM switches efficiently and swiftly. The proposed scheduler approximately provides 100% throughput for scheduling. The proposed algorithm completes the arbitration for N-port VOQ switch with 4-iterative matching. Also the proposed algorithm has a merit for implementing the scheduling algorithm with 1/2 area compared to that of iSLIP scheduling algorithm which is widely used. The performance of the proposed scheduling algorithm is superior to that of iSLIP in 4-iterative matching. The proposed scheduling algorithm was implemented in FPGA and verified on board-level.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.439-446
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• 2004

This paper describes high speed and low power design techniques for an 8-bit 500MSamples/s CMOS 2-step ADC. Instead of the conventional closed-loop architecture, the newly proposed ADC adopts open-loop architecture and uses a reset-switch to reduce loading time in an environment of big parasitic-capacitances of mux-array. An analog-latch is also used to reduce power consumption. Simulation result shows that the ADC has the SNDR of 46.91㏈ with a input frequency of 103MHz at 500Msample/s and consumes 203㎽ with a 1.8V single power supply. The chip is designed with a 0.18mm 1-poly 6-metal CMOS technology and occupies active area of 760${\mu}{\textrm}{m}$*800${\mu}{\textrm}{m}$.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1625-1636
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• 2017

A power electronic transformer (PET) based on the cascaded H-bridge (CHB) and the isolated bidirectional DC/DC converter (IBDC) is capable of accommodating a large scale battery energy storage system (BESS) in the medium-voltage grid, and is referred to as a power electronic transformer based battery energy storage system (PET-BESS). This paper investigates the PET-BESS and proposes a coordinative control strategy for it. In the proposed method, the CHB controls the power flow and the battery state-of-charge (SOC) balancing, while the IBDC maintains the dc-link voltages with feedforward implementation of the power reference and the switch status of the CHB. State-feedback and linear quadratic Riccati (LQR) methods have been adopted in the CHB to control the grid current, active power and reactive power. A hybrid PWM modulating method is utilized to achieve SOC balancing, where battery SOC sorting is involved. The feedforward path of the power reference and the CHB switch status substantially reduces the dc-link voltage fluctuations under dynamic power variations. The effectiveness of the proposed control has been verified both by simulation and experimental results. The performance of the PET-BESS under bidirectional power flow has been improved, and the battery SOC values have been adjusted to converge.