• Title/Summary/Keyword: Active DSRC

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Active DSRC ETC System (능동형 DSRC ETC 시스템)

  • Yi Ji-Hun;Byeon Woo-Sub;You Heung-Ryeol
    • 한국정보통신설비학회:학술대회논문집
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    • 2002.08a
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    • pp.220-230
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    • 2002
  • 고속으로 주행하는 차량으로부터 차량의 일시정지함이 없이 자동으로 통행요금을 징수하기 위한 ETC(Electronic Toll Collection, 통행요금자동징수)서비스는 전용의 무선통신방식, 전자지불수단, 암호화, 영상인식, 실시간제어등의 다양한 기술을 필요로 한다. KT ETC 시스템은 능동형 DSRC(Dedicated Short Range Communication, 단거리전용통신)를 이용한 상용의 ETC 시스템이다. 본 논문에서는 KT ETC 시스템의 개발과 관련하여 핵심 기술인 능동형 DSRC와 ETC 서비스를 위한 스마트카드 기술등을 소개하고, KT ETC 시스템에 고유한 ETC 서비스 처리절차를 소개한다.

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A Study on the Bandwidth of Compatible ETC System (ETC 시스템 주파수 대역 호환에 관한 연구)

  • 정신철;최기수;이병섭
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.13 no.2
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    • pp.115-122
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    • 2002
  • In this paper, we proposed a new technique to be compatible the passive with active ETC system. Now the TTA is making a Standard of the Active DSRC System. So It is necessary to be compatible the developed and running passive ETC system with the developing active ETC system. So we proposed the direct conversion method without performance a decreasing of passive DSRC system using a similar bandwidth of the active ETC system. Simulations carried out and the results show the difference between the conventional and proposed method.

Analysis of the RF Link Design for ETCS and Study on the Communication Zone by the Antenna Beam Pattern (ETCS용 RF 링크 설계와 안테나 빔 패턴에 의한 통신 영역 연구)

  • Yim Choon-Sik;Ha Jae-Kwon;Ahn Dong-Hyun
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.3 no.1 s.4
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    • pp.21-30
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    • 2004
  • This paper describes the design of RF link between RSE and OBU of ETCS and the analysis of the antenna beam pattern to get a proper communication area in the cross direction and traveling direction of lanes. This stage should be performed prior to determination of system requirements of ITS service based on active DSRC. This study is important and fundamental technical analysis to design and implement base station of ETCS.

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A 5.8GHz SiGe Down-Conversion Mixer with On-Chip Active Batons for DSRC Receiver (DSRC수신기를 위한 능동발룬 내장형 5.8GHz SiGe 하향믹서 설계 및 제작)

  • 이상흥;이자열;이승윤;박찬우;강진영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.4A
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    • pp.415-422
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    • 2004
  • DSRC provides high speed radio link between Road Side Equipment and On-Board Equipment within the narrow communication area. In this paper, a 5.8 GHz down-conversion mixer for DSRC communication system was designed and fabricated using 0.8 ${\mu}{\textrm}{m}$ SiGe HBT process technology and RF/LO matching circuits, RF/LO input balun circuits, and If output balun circuit were all integrated on chip. The chip size of fabricated mixer was 1.9 mm${\times}$1.3 mm and the measured performance was 7.5 ㏈ conversion gain, -2.5 ㏈m input IP3, 46 ㏈ LO to RF isolation, 56 ㏈ LO to IF isolation, current consumption of 21 mA for 3.0 V supply voltage.

A 5.8 GHz SiGe Up-Conversion Mixer with On-Chip Active Baluns for DSRC Transmitter (DSRC 송신기를 위한 능동발룬 내장형 5.8 GHz SiGe 상향믹서 설계 및 제작)

  • Lee Sang heung;Lee Ja yol;Kim Sang hoon;Bae Hyun cheol;Kang Jin yeong;Kim Bo woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.4A
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    • pp.350-357
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    • 2005
  • DSRC provides high speed radio link between Road Side Equipment and On-Board Equipment within the narrow communication area. In this paper, a 5.8 GHz up-conversion mixer for DSRC communication system was designed and fabricated using 0.8 m SiGe HBT process technology and IF/LO/RF matching circuits, IF/LO input balun circuits, and RP output balun circuit were all integrated on chip. The chip size of fabricated mixer was $2.7mm\times1.6mm$ and the measured performance was 3.5 dB conversion gain, -12.5 dBm output IP3, 42 dB LO to If isolation, 38 dB LO to RF isolation, current consumption of 29 mA for 3.0 V supply voltage.

A Study on The Design of China DSRC System SoC (중국형 DSRC 시스템 SoC 설계에 대한 연구)

  • Shin, Dae-Kyo;Choi, Jong-Chan;Lim, Ki-Taeg;Lee, Je-Hyun
    • 전자공학회논문지 IE
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    • v.46 no.4
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    • pp.1-7
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    • 2009
  • The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.

Design of 5.8 GHz Patch Array Antenna for FTMS Roadside Equipment (FTMS 기지국용 5.8 GHz 대역 배열 패치 안테나 설계)

  • Kwon, Han-Joon;Lee, Jae-Jun;Lee, Seung-Hwan;Kim, Yong-Deak
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.7 no.4
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    • pp.61-70
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    • 2008
  • This paper designed the antenna for collecting and servicing the traffic information that apply to freeway Traffic Management System, as using DSRC (Dedicated Short Range Communication). Active DSRC is the technology that is using 5.8GHz Radio Frequency to a mean Sequency and there are a lot of the case occurring a physical electric wave shadowing because of the traveling straight of a electric wave. In such inferior communication environment, it constructed the stabilized communication link that can do collecting and servicing the correct traffic information and designed the beam pattern considering the establishment position of the antenna that can apply to various road environments and a communication area. By considering the communication link environment, this paper designed and manufacture the mean frequency of 5.8GHz, the input loss of -17dB in 75MHz bandwidth, the Axial ratio of 1.5:1, and $2{\times}4$ array microstrip antenna which beam pattern have the characteristic of $55^{\circ}$ horizontal half power beam width and $26^{\circ}$elevation half power beam width and the minimum establishment height of the antenna was designed as 14m for avoiding electric wave shadowing on a physical condition between vehicles

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The Design and implementation of a 5.8GHz band LNA MMIC for Dedicated Short Range Communication (단거리전용통신을 위한 5.8GHz대역 LNA MMIC 설계 및 구현)

  • 문태정;황성범;김용규;송정근;홍창희
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.8
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    • pp.549-554
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    • 2003
  • In this paper, we have designed and implemented by a monolithic microwave integrated circuit(MMIC) of a 5.8GHz-band low noise amplifier (LNA) composed of receiver front-end(RFE) in a on-board equipment system for dedicated short range communication. The designed LNA is provided with two active devices, matching circuits, and two drain bias circuits. Operating at a single supply of 3V and a consumption current of 18mA, The gain at center frequency 5.8GHz is 13.4dB, NF is 1.94dB, Input IP3 is -3dBm, S$_{11}$ is -18dB, and S$_{22}$ is -13.3dB. The circuit size is 1.2 $\times$ 0.7 $\textrm{mm}^2$.>.

The Design and implementation of a Low Noise Amplifier for DSRC using GaAs MESFET (GaAs MESFET을 이용한 DSRC용 LNA MMIC 설계 및 구현)

  • Moon, Tae-Jung;Hwang, Sung-Bum;Kim, Byoung-Kook;Ha, Young-Chul;Hur, Hyuk;Song, Chung-Kun;Hong, Chang-Hee
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.61-64
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    • 2002
  • We have optimally designed and implemented by a monolithic microwave integrated circuit(MMIC) the low noise amplifier(LNA) of 5.8GHz band composed of receiver front-end(RFE) in a on-board equipment system for dedicated short range communication using a depletion-mode GaAs MESFET. The LNA is provided with two active devices, matching circuits, and two drain bias circuits. Operating at a single supply of 3V and a consumption current of 18㎃, The gain at center frequency 5.8GHz is 13.4dB, Noise figure(NF) is 1.94dB, Input 3rd order intercept point(lIPS) is 3dBm, and Input return loss(5$_{11}$) and Output return loss(S$_{22}$) is -l8dB and -13.3dB, respectively. The circuit size is 1.2$\times$O.7$\textrm{mm}^2$.EX>.>.

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Development of an Effectiveness Analysis Tool for Freeway Tollgate Entrance Control (고속도로 톨게이트 진입제어용 효과분석 툴의 개발)

  • Lee, Hwan-Pil;Yun, Il-Soo;Oh, Young-Tae;Kim, Soo-Hee
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.11 no.3
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    • pp.1-12
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    • 2012
  • This paper aims at developing an active expressway entrance control effectiveness analysis tool which operators can utilize and manage traffic based on current traffic condition. For this, after identifying the current problems of tollgate-based entrance policy being used, a new set of decision element such as congestion index, decision criteria for congestion, and congestion management unit has been proposed together with the procedure of newly developed tollgate control policy. Three key parts developed are traffic condition identification module, tollgate metering module, and travel speed calculation module. Some measures of effectiveness were also identified and the newly developed effectiveness analysis tool produced better result. According to classification of traffic condition by reference speed as 80km/h, the improved tollgate entrance procedure increased 21.5% in average travel speed compared with Do-Nothing case and also increased 8.8% compared with current entrance control method.