• Plant Breeding and Biotechnology
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• v.5 no.3
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• pp.237-242
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• 2017

AT-hook proteins of plant have shown to be involved in growth and development through the modification of chromatin architecture to co-regulate transcription of genes. Recently, many genes encoding AT-hook protein have been identified and their involvement in senescence delay is investigated. In this study, soybean transgenic plants overexpressing chromatin architecture-controlling ATPG7 gene was produced by Agrobacterium-mediated transformation and investigated for the positive effect on the important agronomic traits mainly focusing on yield-related components. A total of 27 transgenic soybean plants were produced from about 400 explants. $T_1$ seeds were harvested from all transgenic plants. In the analysis of genomic DNAs from soybean transformants, ATPG7 and Bar fragments were amplified as expected, 975 bp and 408 bp in size, respectively. And also exact gene expression was confirmed by reverse transcriptase-PCR (RT-PCR) from transgenic line #6, #7 and #8. In a field evaluation of yield components of ATPG7 transgenic plants ($T_3$), higher plant height, more of pod number and greater average total seed weight were observed with statistical significance. The results of this study indicate that the introduction of ATPG7 gene in soybean may have the positive effect on yield components.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.221-228
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• 2007

In this paper, we propose a new symbolic simulation for scan chain diagnosis to solve the diagnosis resolution problem. The proposed scan chain fault simulation, called the SF-simulation, is able to analyze the effects caused by faulty scan cells in good scan chains. A new scan chain fault simulation is performed with a modified logic ATPG pattern. In this simulation, we consider the effect of errors caused by scan shifting in the faulty scan chain. Therefore, for scan chain diagnosis, we use the faulty information in good scan chains which are not contaminated by the faults while unloading scan out responses. The SF-simulation can tighten the size of the candidate list and achieve a high diagnosis resolution by analyzing fault effects of good scan chains, which are ignored by most previous works. Experimental results demonstrate the effectiveness of the proposed method.

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3226-3235
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• 2000

The more complex and larger semiconductor integraed circuits become, the core important delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults offectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification . First. we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator inthe circuti. Determming enhanced scan flip-flops are based on a fault coverage or a hardware overhead. through the expenment for JSCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan enviroment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.