• The Transactions of the Korea Information Processing Society
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• v.6 no.1
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• pp.167-174
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• 1999

In this paper, we propose the adaptive separated-queueing ATM switching model for the effective processing of the various types of multimedia traffic by virtue of ATM switching network with multiple outlets which is the essential part of B-ISDN. This proposed model employs the dynamically separated buffering mechanism in the processing of two classes of cell, realtime service traffic and non-realtime service traffic, at the output buffer to enhance the overall QoS(Quality of Service). The adopted ATM switch architecture has Batcher-banyan based network, but it uses different topologies and control techniques 6to resolve the cell contention. For the performance evaluation of our proposed method, we have done both analytical modeling and simulation. The both results show that our proposed queueing strategy is quite appropriate to the ATM switch with multiple outlets and can quarantee the QoS requirements of the incoming multimedia traffic.

• Journal of Communications and Networks
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• v.17 no.3
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• pp.286-295
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• 2015

Avionic databuses fulfill a critical function in the connection and communication of aircraft components and functions such as flight-control, navigation, and monitoring. Ethernet-based avionic databuses have become the mainstream for large aircraft owning to their advantages of full-duplex communication with high bandwidth, low latency, low packet-loss, and low cost. As a new generation aviation network communication standard, avionics full-duplex switched ethernet (AFDX) adopted concepts from the telecom standard, asynchronous transfer mode (ATM). In this technology, the switches are the key devices influencing the overall performance. This paper reviews the avionic databus with emphasis on the switch architecture classifications. Based on a comparison, analysis, and discussion of the different switch architectures, we propose a new avionic switch design based on a time-division switch fabric for high flexibility and scalability. This also merges the design concept of space-partition switch fabric to achieve reliability and predictability. The new switch architecture, called space partitioned shared memory switch (SPSMS), isolates the memory space for each output port. This can reduce the competition for resources and avoid conflicts, decrease the packet forwarding latency through the switch, and reduce the packet loss rate. A simulation of the architecture with optimized network engineering tools (OPNET) confirms the efficiency and significant performance improvement over a classic shared memory switch, in terms of overall packet latency, queuing delay, and queue size.

• The KIPS Transactions:PartC
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• v.10C no.4
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• pp.463-470
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• 2003

Many types of switching fabrics have been proposed for use in ATM networks. Multistage Interconnection Networks (MINs) constitute a large class of ATM switching systems that are widely used in today´s internetworking. One of the most veil-known types of multistage networks is the banyan network. The banyan network is attractive for its simple routing scheme and low hardware complexity, but its throughput is very limited due to internal blocking and output contention. In this paper, we propose an input-buffered dual-banyan switch model with multiple switching fabric between switch input and output to avoid internal and Head-of Line blocking. By performance analysis and simulation, we show that our model has a lower ceil delay and 96% throughput which is much better than other banyan-type switch architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.122-131
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• 2000

In this paper, we propose a cell scheduling algorithm for input queueing ATM switch. The input queueing architecture is attractive for building an ultra-high speed ATM (Asynchronous Transfer Mode) switch. We proposea WMUCS (Weighted Matrix Unit Cell Scheduler) based on the MUCS which resolves HOL blocking and outputport contention. The MUCS algorithm selects an optimal set of entries as winning cells from traffic matrix (weightmatrix). Our WMUCS differs from the MUCS in generating weight matrices. This change solves the starvationproblem and it reduces the cell loss variance. The performance of the proposed algorithm is evaluated by thesimulation program written in C++. The simulation results show that the maximum throughput, the average celldelay, and the cell loss rate are significantly improved. We can see that the performance of WMUCS is excellentand the cost-effective implementation of the ATM switch using proposed cell scheduling algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.4
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• pp.575-581
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• 1998

In order to accommodate current accelerated growth in customers and traffic. Internet has faced the demand to scale its network dimension both in size and bandwidth, and new service provisioning. One way to solve this problem is to forward If packets based on ATM switching technology. This paper briefly explained technical tasks to apply this If switching technique in ATM networks for building Internet backbone, and presented the directions to approach these tasks. Those tasks are scalability, ATM VC setup and mapping between VC and IP packet flow, traffic management and traffic engineering, multicast, and finally ATM switch architecture to provide multiservice.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.7
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• pp.1393-1398
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• 2003

In this paper, we propose a new switch architecture with one schedule at k-time slots, which k means the allocated time slots for each schedule. A conventional switch system uses a single time slot per each schedule but the proposed switch system uses multiple time slots per each schedule. Both the conventional switch md the proposed switch have same throughput but our switch system occupies multiple cell time slots per each schedule and hence can be implemented in scheduler of simple circuitry compared to the conventional switch. The proposed scheduling method for switch system will be applicable in switch system with high-speed data link rate.

• The Transactions of the Korea Information Processing Society
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• v.6 no.6
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• pp.1581-1589
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• 1999

In B-ISDN(Broadband Integrated Services Digital Networks), the efficient implementation of multicast function is very important since the demand for distributed type of service such as VOD(Video On Demand) system is expected to grow. In this paper, the multicast performance characteristics of fully-interconnected switch fabric used for our research is the proper architecture for a small-sized switch element, and it uses bit addressing method for addressing scheme and thus it is easy to implement multicast function without adding a function block. To incorporate the bursty nature of traffic in ATM networks, we used IBP(Interrupted Bernoulli Process) model as an input traffic model. We presented and analyzed the simulation results in terms of the multicast operation of the switch. Based. on this study, it its analyzed that congestion avoidance may be feasible if we use a proper traffic control scheme by finding an overload point due to multicast.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.8
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• pp.30-41
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• 2001

In this paper, the architecture of Dynamic GSMP V3(General Switch Management Protocol Version 3), an open interface protocol with resource management functions for efficient IP service on ATM over MPLS, is proposed and implemented in hardware. And we compare and analyze the proposed GSMP with the GSMP under standardization process in terms of CLR (Cell Loss Rate). We design the Slave block of the Dynamic GSMP V3 using SAM-SUNG SoG $0.5{\mu}m$ process, which performs functions for switch connection control in the ATM Switch. In order to compare difference performanaces between the proposed method and the conventional one, we conducts simulations using the minimum buffer search algorithm with random cell generation. The exponential results show that the proposed method leads to performance enhancement in CLR.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2850-2861
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• 1996

This paper describes the design of AATM switch LIS of shared buffer type with linked-list architecture to control memory access. The proposed switch LSI consists of the buffer memory, controller and FIFO memory blocks and two special circuits to avoid the cell blocking. One of the special circuit is a new address control scheme with linked-list architecture which maintains the address of buffer memory serially ordered from write address to read address. All of the address is linked as chain is operated like a FIFO. The other is slip-flag register it will be hold the address chain when readaddress missed the reading of data. The circuits control the buffer memory efficiently and reduce the cell loss rate. As a result the designed chip operates at 33ns and occupied on 2.7*2.8mm$^{2}$ using 0.8.mu.m CMOS technology.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.441-443
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• 1998

본 논문은 유무선 환경에서 ATM 멀티캐스트 서비스를 제공하기위한 방안으로서{{{{ { SM}^{2 }A }}}} 를 제안한다. 기존의ATM 멀티캐스트 서비스는 ATM자체의 제약으로 멀티캐스트 서비스가 제한적이며 비효율적이다. 한편, ATM의 중용한 응용으로서 인터넷서비스를 심각하게 고려해야하는데 {{{{ { SM}^{2 }A }}}}는 특히 인터넷 서비스를 제공하는데 적합한 구조를 갖도록 설계되었다.{{{{ { SM}^{2 }A }}}}는 기본적으로 양방향성 공유트리방식인 CBT(Core Based Tree)구조를 갖되 각 지역망 (Regional Network)에서 자체적인 코어스위치( Core Switch)를 보유함으로써 결과적으로 다중 코어 구조를 갖는다. 각 지역망을 잇기 위하여 PNNI 프로토콜을 이용하며 PGL(Peer Group Leader)에 가상 루트(Virtual Root) 및 가상 리프(Virtual Leaf)의 개념을 새로 도입한다. 멀티캐스트 통신의 경우 가장 문제되는 것이 셀끼워넣기(Interleaving)문제인데.{{{{ { SM}^{2 }A }}}}에서는 ITU-T표준 ATC(ATM Transfer Capability)인 ABT/IT(ATM Block Transfer/Immediate Transmission)