• The Transactions of the Korea Information Processing Society
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• v.6 no.1
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• pp.148-158
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• 1999

ABR traffic form ATM LAN is controlled through RM cell, and the interface function to public ATM network is necessary to provide ABR service efficiently. This paper presnets new interface architecture, which is based on "Projected Node" [6]. using AIPU(ABR Interface Proxy Unit) to support ABR traffic streams incoming from ATM LAN in the public ATM network. For the efficient interworking, the AIPU has designed for interworking functions with ERICA switch mechanism. Conventional ERICA switch mechanism specified in TM 4.0 is basically used for short distance comparative to public network, however AIPU adopts the novel control mechanism to cover logng roud trip time (RTT). To improve the problems and to provide a dynamic range of UCI(Update Count Interval), this paper proposes, a novel control scheme, DUCI ( Dynamic Update Count Interval. And the paper shows inefficiencies of ERICA mechanism with fixed UCI through the simulation results, and represents the performance enhancement of DUCI mechanism developed to adjust the update count interval dynamically.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.4
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• pp.10-19
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• 1998

With the advent of high-speed networks, the increasingly stringent performance requeirements are being placed on the underlying switching systems. Under these circumstances, simulation methods for evaluating the performace of such a switch requires vast computational cost and accordingly the importance of anlytical methods increases. In general, the performance analysis of a switch architecture is also a very difficult task in that the conventional queueing system such as switching systems, which consists of a large numbe of queues which interact with each other in a fiarly complicated manner. To overcome these difficulties, most of the past research results assumed that multiple queues become decoupled as the switch size grows unboundely large, which enables the conventional queueing theory to be applied. In this apepr, w analyze a non-blocking space-division ATM swtich with input queueing, and prove analytically the pheonomenon that virtual queues formed by the head-of-line cells become decoupled as the switch size grows unboundedly large. We also establish various properties of the limiting queue size processes so obtained and compute the maximum throughput associated with ATM switches with input queueing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.12
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• pp.2828-2833
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• 1997

In this paepr, we have proposed an enhanced TDM with WDM hybrid photonic switching architecture, which has much simpler configuration and requires less hard ware. the basic module consists of arrayed waveguide grating (AWG) for wavelength division, compressor and fiber delay lines for time division. When compared with other systems, we proved that the proposed switch is suitable for large capacity photonic switching system due to less complexity and lower cost in implementation than the previous ones.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1323-1333
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• 1997

In this paper, we propose an efficient architecture for a high-speed cell concentrator/distributor(HCCD) in an ATM(Asynchronous Transfer Mode) switch and by analyzeing the simulation results evaluate the performance of the proposed architecuture. The proposed HCCD distributes cells from a switch link to local processors, or concentrates cells from local processor s to a switch link. This design is to guarntee a high throughput for the IPC (inter-processor communication) link in a distributed ATM switching system. The HCCD is designed in a moudlar architecture to provide the extensibility and the flexibility. The main characteristics of the HCCD are 1) Adaption of a local CPU in HCCD for improving flexibility of the system, 2) A cell-baced statistical multiplexing function for efficient multiplexing, 3) A cell distribution function based on VPI(Virtual Path Identifier), 4) A bypassing capability for IPC between processor attached to the same HCCD, 5) A multicasting capability for point-to-multipoint communication, 6) A VPI table updating function for the efficient management of links, 7) A self-testing function for detecting system fault.

• Journal of Korean Institute of Industrial Engineers
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• v.19 no.1
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• pp.47-59
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• 1993

Recently, Broadband ISDN(B-ISDN) has received increased attention as a communication architecture which can support multimedia applications. Also, Asynchronous Transfer Mode(ATM) is considered as a promising technique to transfer and switch various kinds of media, such as telephone speech, data and motion video. Comparisons among a variety of ATM switching systems which have already been proposed will provide quite useful information for the new ATM switching system design. To facilitate the comparison, we introduce the design requirements and classification criteria for the ATM switch, and propose a performance analysis model for the Banyan network which is the basic switching fabric of most multi-stage ATM switching systems. The model is based on the standard discrete-time Markov chain analysis and can be conveniently used for extensive Banyan network analysis. The computational results are also presented.

• The KIPS Transactions:PartC
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• v.8C no.2
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• pp.141-154
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• 2001

MOBAS는 규칙적인 모듈로 구성되어 있어 확장이 용이하며, VLSI 구현 시 고집적화 할 수 있고, 각 모듈간에 동기를 맞추기 쉬울 뿐 아니라, 단일 종류의 칩으로 중앙 스위치 구조를 구성할 수 있다. Modified MOBAS(Multicast Output Buffered ATM Switch)는 MOBAS와 유사한 구조를 가지지만 스위치 모듈(SM : Switch Module)의 구조에서 차이를 보이며 적은 스위치소자(SWE : Switch Element)를 사용한다. 위성 통신에서 스위치의 크기뿐 아니라 고장감내 특성도 스위치를 디자인하는데 필요한 중요한 요소이다. 본 논문에서는 Modified MOBAS의 고장 특성을 분석하고 이에 적합한 Detection 기법 및 Location 기법을 제안하였다. 또한 스위치 모듈구조를 변형하여 Modified MOBAS에 비해 약간의 스위치 소자를 더 사용하지만 MOBAS에 비해서는 적은 스위치 소자를 사용할 뿐 아니라, MOBAS와 같이 단일 고장 하에서 성능의 저하가 거의 없다.

• Journal of the Korea Society of Computer and Information
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• v.6 no.1
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• pp.74-81
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• 2001

In this paper. the architecture of a high-speed ATM router using ATM switch is studied and the performance of the high-speed ATM router is analyzed through simulation. The high-speed ATM router using ATM switch is able to reduce the load of router and the processing time of a packet in the router. The size of router buffers has been studied through simulation processes for the analysis of performance capacity in due course of making changes in routing time(RT), which is the performance capacity parameters of high-speed ATM routers, flow table size(FS), flow live time(FT) and input circuit efficiencies. The result of this study can be used as the source material for analyzing the suitability of equipment in upgrading networks and applying high-speed ATM routers by using ATM switches.

• ETRI Journal
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• v.18 no.4
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• pp.229-244
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• 1997

Realization of the economical, reliable, and efficient ATM interface block becomes an important key to development of the ATM switching system when we consider new issues raised recently. In this paper, we summarize requirements for the ATM interface block and present the UNI (User Network Interface)/NNI (Network Node Interface) architecture to meet these requirements. We also evaluate the performance of the multiplexer adopting the various multiplexing schemes and service disciplines. For ATM UNI/NNI interface technologies, we have developed a new policing device using the priority encoding scheme. It can reduce the decision time for policing significantly. We have also designed a new spacer that can space out the clumped cell stream almost perfectly. This algorithm guarantees more than 99 % conformance to the negotiated peak cell rate. Finally, we propose the interface architecture for accommodation of the ABR (Available Bit Rate) transfer capability. The proposed structure that performs virtual source and virtual destination functions as well as a switch algorithm can efficiently accommodate the ABR service.

• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.115-123
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• 2002

This thesis proposes a new type of Input-Output Buffered ATM Switch which employs an arbiter and its performance under different traffic conditions studied. The proposed switch is designed with a view to exploit the architecture and other characteristics of the arbiter. The primary aim of the proposed switch is the elimination, or at least, the reduction of HOL blocking phenomenon which occurs in the simple input buffered switch. Several HOL arbitration algorithms have been proposed for this purpose in the literature. The proposed switch attempts to reduce the HOL blocking as it uses the arbiter and the buffer at the output port in an effective manner. The arbiter is designed to work with Three Phase Algorithm which is one of the many well known HOL arbitration algorithms. The Proposed switch acquires control over priority transmission through the REQ signal. As the signals are transmitted to the arbiter, the latter controls the one which is sent by the input buffer. Computer simulation results have been provided to demonstrate the effectiveness of the Proposed switch under uniform traffic conditions.

• Journal of the Korea Society of Computer and Information
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• v.8 no.2
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• pp.97-105
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• 2003

This thesis proposes a new type of Input-Output Buffered ATM Switch which employs an arbiter and its performance under different traffic conditions studied. The proposed switch is designed with a view to exploit the architecture and other characteristics of the arbiter The primary aim of the proposed switch is the elimination, or at least, the reduction of HOL blocking phenomenon which occurs in the simple input buffered switch. Several HOL arbitration algorithms have been proposed for this purpose in the literature. The Proposed switch attempts to reduce the HOL blocking as it uses the arbiter and the buffer at the output Port in an effective manner. The arbiter is designed to work with Three Phase Algorithm which is one of the many well known HOL arbitration algorithms . The proposed switch acquires control over priority transmission through the REd signal. As the signals are transmitted to the arbiter, the latter controls the one which is sent by the input buffer. Computer simulation results have been provided to demonstrate the effectiveness of the proposed switch under non-uniform random traffic conditions.