• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.1
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• pp.162-172
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• 1997

In this paper, we investigated the performance of a binary feedback switch algorithm for the ABR(Available Bit Rate) service in ATM networks. A binary feedback switch is also called EFCI(Explicit Forward Congestion Indication) switch and can be classificed into input cell processing(IP) scheme according to processing methods for the EFCI bit in data-cell header. We proposed two implementation methods for the binary feedback switch according to EFCI-bit processing schemes, and analyzed the ACR(Allowed Cell Rate) of source and the queue length of switch for each scheme in steady state. In addition, we derived the upper and lower bounds for maximum and minimum queue lengths, respectively, and investigated the impact of ABR parameters on the queue length.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.205-208
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• 2002

An existing ATM switch fabric uses VPI(Virtual Path Identifier) and VCI(Virtual Channel Identifier) information to route ATM cell. But AAL type 2 switch which efficiently processes delay-sensitive, low bit-rate data such as a voice routes the ATM cell by using CID(Channel Identification) field in addition to VPI and VCI. In this paper, we research the AAL type 2 switch that performs the process of CPS packet. The Receive unit extracts the CPS packet from the inputted ATM cell. The designed receive unit consists of input FIFO, r)( status table, CAM(Content Addressable Memory), new CID table and partial packet memory. Also the designed receive unit supports the PCI interface with host processor. The receive unit is implemented in Xilinx FPGA and operates at 72MHz.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.4
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• pp.10-19
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• 1998

With the advent of high-speed networks, the increasingly stringent performance requeirements are being placed on the underlying switching systems. Under these circumstances, simulation methods for evaluating the performace of such a switch requires vast computational cost and accordingly the importance of anlytical methods increases. In general, the performance analysis of a switch architecture is also a very difficult task in that the conventional queueing system such as switching systems, which consists of a large numbe of queues which interact with each other in a fiarly complicated manner. To overcome these difficulties, most of the past research results assumed that multiple queues become decoupled as the switch size grows unboundely large, which enables the conventional queueing theory to be applied. In this apepr, w analyze a non-blocking space-division ATM swtich with input queueing, and prove analytically the pheonomenon that virtual queues formed by the head-of-line cells become decoupled as the switch size grows unboundedly large. We also establish various properties of the limiting queue size processes so obtained and compute the maximum throughput associated with ATM switches with input queueing.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.83-92
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• 1997

Multipath ATM switch architectures have the potential to accommodate easily the design of high-speed and large capacity ATM switches which can handle a very large amount of switching throughputs. However, the multipath architecture inevitably encounters out-of-sequence problems. We propose a multipath switch model to analyze the out-of-sequence phenomenon. And we analyze the out-of-sequence performance dependency on the architecture parameters : the number of multipath, the trunk utilization, the switch size, and the number virtual channels/trunk. Indexing terms : ATM switch, Multipath archltecture, Out-of-sequence performance, Cell sequence integrity, Analytical model.

• The Transactions of the Korea Information Processing Society
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• v.6 no.1
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• pp.148-158
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• 1999

ABR traffic form ATM LAN is controlled through RM cell, and the interface function to public ATM network is necessary to provide ABR service efficiently. This paper presnets new interface architecture, which is based on "Projected Node" [6]. using AIPU(ABR Interface Proxy Unit) to support ABR traffic streams incoming from ATM LAN in the public ATM network. For the efficient interworking, the AIPU has designed for interworking functions with ERICA switch mechanism. Conventional ERICA switch mechanism specified in TM 4.0 is basically used for short distance comparative to public network, however AIPU adopts the novel control mechanism to cover logng roud trip time (RTT). To improve the problems and to provide a dynamic range of UCI(Update Count Interval), this paper proposes, a novel control scheme, DUCI ( Dynamic Update Count Interval. And the paper shows inefficiencies of ERICA mechanism with fixed UCI through the simulation results, and represents the performance enhancement of DUCI mechanism developed to adjust the update count interval dynamically.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.39-47
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• 1998

This paper describes high-speed pipelined memory architecture for a shared buffer ATM switch. The memory architecture provides high speed and scalability. It eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. It consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of the designed pipelined memory is 4 ns with 5 V V$\_$dd/ and 25$^{\circ}C$. It is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 $\mu\textrm{m}$ 2-metal 1-poly CMOS technology.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.115-118
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• 1998

ATM(Asynchronous Transfer Mode)을 기반으로한 BSC(Base Station Controller)를 이용한 무선 이동통신망에서는 크게 MSC, BSC, BTS로 구성 되어진다. BSC는 MSC(Mobile Switch Center)와의 STM-1급 (155.52Mbps) 정합이 이루어지며, 여러 BTS(Base Transceiver Subsystem)와 T1(1.544Mbps)/E1(2.048Mbps)급 정합이 이루어져 호연결, 관리, 제어 및 MT(Mobile Terminal)의 soft-handoff를 담당한다. BSC내의 저속 가입자 I/F에서는 BTS와 BSC내의 ATM switch와의 정합을 수행하면서 VPI/VCI변환, BSC 내부 cell format으로 변환, 그리고 UPC(Usage Parameter Control)등이 이루어진다. 본 논문에서는 ATM switch를 이용한 BSC 내부의 저속 가입자 I/F의 구현에 관해서 살펴본다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.5
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• pp.429-432
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• 2004

In this paper, we propose a new sorting algorithm for ATM switch with a shared buffer which has a sequencer architecture with single queue. The proposed switch performs a sorting procedure of ATM cell based on the output port number of ATM cell with hardware implementation. The proposed architecture has a single buffer physically but logically it has function of multi-queue which is designed at most to control the conflicts in output port. In the future, this architecture will take various applications for routing switch and has flexibility for the extension of system structure. therefore, this structure is expected on good structure in effective transmission.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.119-130
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• 1996

This paper is the part I of the full study about improved structure of fully interconnected ATM switch to develop the small sized switch element and practical implemention of switch network. This part I paper describes about proposed switch structure, performance evaluations and some of considerations to practical implementation. The proposed structure is constructed of two step buffering scheme in a filtered multiplexer. First step buffering is carried out by small sized dedicated buffers located at each input port. And second step buffering is provided by a large sized common buffer at the output port. To control bursty traffic, we use speed up factor in multiplexing and priority polling according to the levels of buffer occupancy. Proposed structure was evaluated by computer simulation with two evaluation points. One is comparision of multiplexing discipline between hub polling and priority polling. The ogher is overall which should be considered to improve the practical implementation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.68-77
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• 1996

In this paper, we investigate the effect of a LAN traffic on the performance of a shared buffer ATM switch andIWF (interworking function )on a LAN environment through simulations. Firstly, the delay and the buffer occupancy of the switch and IWF are mesured according to the proportion of the LAN traffic to the traffic generated by gernoulli process. Secondly, we investigate the behavior of the switch in the case that LAN traffic is concentrated to a connectionless server, and the effect of LAN traffic shaping at IWF on the delay and the buffer occupancy of the switch.