• Journal of Power Electronics
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• 제16권5호
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• pp.1650-1660
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• 2016

This paper proposes a compensator to eliminate the DC bias of inductor current. This method utilizes an average-current sensing technique to detect the DC bias of inductor current. A small signal model of the DC bias compensation loop is derived. It is shown that the DC bias has a one-pole relationship with the duty cycle of the left side leading lag. By considering the pole produced by the dual active bridge (DAB) converter and the pole produced by the average-current sensing module, a one-pole-one-zero digital compensation method is given. By using this method, the DC bias is eliminated, and the stability of the compensation loop is ensured. The performance of the proposed compensator is verified with a 1.2-kW DAB converter prototype.

• Journal of Power Electronics
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• 제16권3호
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• pp.823-831
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• 2016

A high-efficiency method is proposed to suppress magnetic core imbalance in phase-shifted full-bridge (PSFB) converters. Compared with conventional solutions, such as controlling peak current mode (PCM) or adding DC blocking capacitance, the proposed method has several advantages, such as lower power loss and smaller size, because the additional current sensor or blocking capacitor is removed. A time domain model of the secondary side is built to analyze the relationship between transformer core imbalance and cathode voltage of secondary side rectifiers. An approximate control algorithm is designed to achieve asymmetric phase control, which reduces the effects of imbalance. A 60 V/15 A prototype is built to verify the proposed method. Experimental results show that the numerical difference of primary side peak currents between two adjacent cycles is suppressed from 2 A to approximately 0 A. Meanwhile, compared with the PCM solution, the efficiency of the PSFB converter is slightly improved from 93% to 93.2%.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(4)
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• pp.199-202
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• 2001

A current TV-OUT format is quite different from that of HDTY or PC monitor in encoding techniques. In other words, a conventional analog TV uses interlaced display while HDTV or PC monitor uses Non-interlaced / Progressive-scanned display. In order to encode image signals coming from devices that takes interlaced display format for progressive scanned display, a hardware logic in which scanning and interpolation algorithms are implemented is necessary. The ELA (Edge-Based Line Average) algorithm have been widely used because it provided good characteristics. In this study, the ADI(Adaptive De-interlacing Interpolation) algorithm using to improve the algorithm which shows low quality in vertical edge detections and low efficiency of horizontal edge lines. With the De-interlacing ASIC chip that converts the interlaced Digital YUV to De-interlaced Digital RGB is designed. The VHDL is used for chip design.

• Tribology and Lubricants
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• 제29권3호
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• pp.143-148
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• 2013

In this study, several sensor parts used to obtain better signal stability are designed, a separate control circuit for the sensor is developed, and the results obtained using this control circuit are analyzed. The capacitances of the whole sensor system are measured using the control circuit connected to an improved flexible printed circuit board and an asymmetric dual sensor coated with a ceramic material. To realize good discrimination for a small change in the measured capacitance as the engine oil deteriorates, a commercial application-specific integrated circuit is installed on the control circuit as a capacitance-to-digital converter. The absolute error of a measured signal is found to be approximately ${\pm}4fF$.

• Journal of Positioning, Navigation, and Timing
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• 제4권3호
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• pp.115-122
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• 2015

Global Positioning System (GPS) is used in various fields such as communications systems, transportation systems, e-commerce, power plant systems, and up to various military weapons systems recently. However, GPS receiver is vulnerable to jamming signals as the GPS signals come from the satellites located at approximately 20,000 km above the earth. For this reason, various anti-jamming techniques have been developed for military application systems especially and it is also required for commercial application systems nowadays. In this paper, we proposed a dual-channel Global Navigation Satellite System (GNSS) RF ASIC for digital pre-correlation anti-jam technique. It not only covers all GNSS frequency bands, but is integrated low-gain/attenuation mode in low-noise amplifier (LNA) without influencing in/out matching and 14-bit analogdigital converter (ADC) to have a high dynamic range. With the aid of digital processing, jamming to signal ratio is improved to 77 dB from 42 dB with proposed receiver. RF ASIC for anti-jam is fabricated on a 0.18-μm complementary metal-oxide semiconductor (CMOS) technology and consumes 1.16 W with 2.1 V (low-dropout; LDO) power supply. And the performance is evaluated by a kind of test hardware using the designed RF ASIC.

• 전자공학회논문지A
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• 제33A권6호
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• pp.32-41
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• 1996

We propose the improved GMSK (gaussian-filtered minimum shift keying) quadrature modulator using the FIR(finite impulse response )filter whose coefficients are obtained form the differnce of phase response, and design its ASIC (applicaton specific integrated circuit) which can be used for GSM (global system for mobile communication) digital cellular system and DCS 1800 (digital cellular system at 1800MHz) personal communication system. Input data become quantized I and Q channel 10 bit signal through cosine and sine ROM mapping after being filtered by the FIR filter whose normalized bandwidth is 0.3 and designed by considering intersymbol interference as well as sampling ratio. These two signals become the GMSK modulated I and Q channel signal through DAC (digital-to-analog converter) and 7th order analog chebyshev LPF(low pass filter) respectively. The difference between the ideal analog signal and its digitized signal is analyzed in terms of sampling noise, quantization noise, truncation noise and coefficient noise. And the effect of the LPF following the DAC is considered. The ASIC design of the GMSK quadrature modulator is also confirmed by an experiment.

• 한국통신학회논문지
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• 제32권11C호
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• pp.1102-1110
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• 2007

본 논문에서는 기존의 정진폭 다중 부호 이진 직교 (CAMB: Constant-Amplitude Multi-code Biorthogonal) 변조 이론을 적용한 변복조기를 프로그래밍 가능한 게이트 배열 (FPGA: Field-Programmable Gate Array)을 사용하여 설계하고 시스템 온 칩 (SoC: System on Chip)으로 구현하였다. 이 변복조기는 FPGA을 이용하여 타겟팅 한 후 보드실험을 통해 설계에 대한 충분한 검증을 거쳐 주문형 반도체 (ASIC: Application Specific Integrated Circuit) 칩으로 제작되었다. 이러한 12Mbps급 모뎀의 SoC를 위하여 ARM (Advanced RISC Machine)7TDMI를 사용하였으며 64K바이트 정적 램 (SRAM: Static Random Access Memory)을 내장하였다. 16-비트 PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus) 1.1, 16C550 Compatible UART (Universal Asynchronous Receiver/Transmitter) 등 다양한 통신 인터페이스를 지원할 뿐 아니라 ADC (Analog to Digital Converter)/DAC (Digital to Analog Converter)를 포함하고 있어 실제 현장에서 쉽게 활용될 수 있을 것으로 기대된다.

• 대한전자공학회논문지SD
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• 제46권10호
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• pp.31-39
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• 2009

본 논문은 전력선 통신용(PLC) SoC ASIC으로 내장된 Analog Front-end(AFE)를 바탕으로 낮은 소비 전력과 저 가격을 달성할 수 있었으며, CMOS공정으로 구현된 AFE와, 1.8V동작의 Core Logic구동용 LDO, ADC, DAC와 IO pad를 구동하기 위한 LDO로 구성되어 있다. AFE는 Pre-amplifier, Programmable gain Amplifier와 10bit ADC의 수신 단으로 구성되며, 송신 단은 10bit differential DAC, Line Driver로 구성되어 있다. 본 ASIC은 0.18 um 1 Poly 5 Metal CMOS로 구현 되었으며, 동작전압은 3.3 V단일 전원만 사용하였고, 이때 소모 전력은 대기 시에 30mA이며, 동작 시 전력은 300mA으로 에코 디자인 요구를 만족하게 하였다. 본 칩의 Chip size는 $3.686\;{\times}\;2.633\;mm^2$ 이다.

• Tribology and Lubricants
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• 제29권2호
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• pp.77-84
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• 2013

A small engine-oil-deterioration detection sensor was developed and installed at the tip of a dipstick gage. The sensor part was manufactured using printed circuit board (PCB) manufacturing technology. A set of sensor covers was installed in order to protect the sensor and realize good signal stability. The small engine-oil-deterioration detection sensor system comprised a dual sensor having etched copper electrodes coated with gold and ceramic, a flexible PCB (FPCB) acting as electric wire, and a dummy PCB with only a lock connector. The sensor can easily be installed by insertion through the guide tube of a dipstick gage. Thus, a driver can easily handle it without further installation equipment. The sensor can determine the level of deterioration in the engine oil by estimating the corresponding dielectric constant of the engine oil.

• 한국통신학회논문지
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• 제22권8호
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• pp.1774-1781
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• 1997

본 논문은 잔류 측대파(vestigial sideband; VSB) 변조를 이용한 CATV 및 HDTV에서 주파수 및 위상 동기 루프 (frequency & phase lock loop; FPLL)의 완전 디지털 구현을 위한 알고리듬과 하드웨어 구조를 제안한다. 미국의 대연합(Grand-Alliance)에서 제안된 VSB 변조를 위한 CATV 및 HDTV 수신기는 아날로그 신호처리를 통하여 반송파 복구를 수행한다. 그러므로 향후 단열 칩 ASIC 개발에 상당한 부담을 주는 구조이다. 본 논문에서는 VSB 변조 방식의 이러한 문제점을 해결하기 위하여 수신된 신호를 기저 대역 근처의 IF 신호로 떨어뜨린 후 아날로그-디지털(AD) 변환을 통하여 모든 신호처리를 디지털 영역에서 할 수 있는 FPLL 구조를 제안한다. 제안된 시스템은 주파수 풀-인(pull-in) 영역이 -200KHz- +250KHz 정도의 우수한 성능을 보여준다. 그리고 위상 잡음의 영향을 최소화 하면서 빠른 포착 성능을 유지하기 위하여 루프 필터의 대역폭을 적응적으로 가변하는 특징을 가진다.