• Asian Pacific Journal of Cancer Prevention
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• v.14 no.4
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• pp.2265-2268
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• 2013

Several lines of evidence indicate that cancer is a multistep process. To survey the mechanisms involving gene alteration and miRNAs in adrenocortical cancer, we focused on transcriptional factors as a point of penetration to build a regulatory network. We derived three level networks: differentially expressed; related; and global. A topology network ws then set up for development of adrenocortical cancer. In this network, we found that some pathways with differentially expressed elements (genetic and miRNA) showed some self-adaption relations, such as EGFR. The differentially expressed elements partially uncovered mechanistic changes for adrenocortical cancer which should guide medical researchers to further achieve pertinent research.

• IE interfaces
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• v.9 no.3
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• pp.72-80
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• 1996

As the fiber optic technology is rapidly being deployed in telecommunication networks, particular emphasis is placed on the survivability in designing networks. Most of the survivable network design models proposed to date have connectivity constraints, which cannot precisely define a network topology owing to the multiplicity of feasible ones. In this paper, we propose a k-link survivable network design model incorporating traffic-based survivability constraints which restrict the lost traffic due to a network failure under a prescribed level. Our model is shown to include the existing connectivity models as special cases. Then we present its integer programming formulation, analyze the structural properties, and develop a heuristic for obtaining low cost survivable networks.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.634-637
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• 1997

This paper is on the research and development of new SIV(Static Inverter) using IGBT(Insulated Gate Bipolar Transistor) semiconductor for a wide range of electric railway applications. For the simplification and higher controllability, the direct PWM control method with 3level inverter topology was adopted. In the new SIV system, the cost as well as bulk and weight was appreciably reduced about 40% lower than those of conventional SIV, the electrical efficiency was increased above 95% and the audible noise level was less than 65dB. In addition, the THD(Total Harmonic Distortion) factor was below 5% and the voltage fluctuation on a transient state was below 10%.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1725-1734
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• 2016

This paper presents a novel seven-level (7L) voltage source converter for high-power medium-voltage applications. The proposed topology is an H-bridge connection of two nested neutral-point clamped (NNPC) converters and is referred to as an HNNPC converter. This converter exhibits advantageous features, such as operating over a wide range of output voltages, particularly for 10-15 kV applications, without the need to connect power semiconductors in series; high-quality output voltage; and fewer components relative to other classic seven-level topologies. A novel sinusoidal pulse width modulation technique is also developed for the proposed 7L-HNNPC converter to control flying capacitor voltages. One of the main features of the control strategy is the independent application of control to each arm of the converter to significantly reduce the complexity of the controller. The performance of the proposed converter is studied under different operating conditions via MATLAB/Simulink simulation, and its feasibility is evaluated experimentally on a scaled-down prototype converter.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.2
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• pp.846-864
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• 2017

Software Defined Network (SDN) realizes management and control over the underlying forwarding device, along with acquisition and analysis of network topology and flow characters through south bridge protocol. Data path Identification (DPID) is the unique identity for managing the underlying device, so forged DPID can be used to attack the link of underlying forwarding devices, as well as carry out DoS over the upper-level controller. This paper proposes a dynamic defense method based on Client-Puzzle model, in which the controller achieves dynamic management over requests from forwarding devices through generating questions with multi-level difficulty. This method can rapidly reduce network load, and at the same time separate attack flow from legal flow, enabling the controller to provide continuous service for legal visit. We conduct experiments on open-source SDN controllers like Fluid and Ryu, the result of which verifies feasibility of this defense method. The experimental result also shows that when cost of controller and forwarding device increases by about 2%-5%, the cost of attacker's CPU increases by near 90%, which greatly raises the attack difficulty for attackers.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.1-10
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• 2010

This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to $V_{dd}$. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 MHz. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.2
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• pp.53-58
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• 2013

A Fat-Tree topology has multiple paths between any pair of hosts. The delay for the multiple paths with an equal number of hops depends mainly on the queuing delay. However, most of the existing load-balancing schemes do not sufficiently exploit the characteristics of Fat-Tree. In most schemes load-balancing is performed at a flow level. Packet-level load-balancing schemes usually require the availability of special transport layer protocols to address packet reordering. In this paper, we propose a new packet-level load-balancing scheme which can enhance network utilization while minimizing packet reordering in Fat-Trees. Simulation results show that the proposed scheme provides as high TCP throughput as a randomized flow-level Valiant load balancing scheme for a best case.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.2
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• pp.116-121
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• 2009

Distributed power systems (DPSs) has been widely used various industrial/military applications due to their various advantages. Furthermore, the "All electric" concept, in conjunction with DC DPS, appears to be more advanced and mature in the AEV(All-Electric Vehicular) industry. Generally, AEV carry many loads with varied functions. However, there may be large pulsed loads with short duty ratios which can affect the normal operation of other loads. In this paper, a converter with spilt capacitors and a simple adaptive controller is proposed as a active damping device to mitigate the voltage transients on the bus. The proposed converter allows the smaller capacitive storage. In addition, the proposed control approach has the advantage of requiring only one sensor and performing both the functions of mitigating the voltage bus transients and maintaining the level of energy stored. The control algorithm has been implemented on a TMS320F2812 Digital Signal Processor (DSP). Simulation and experimental results are presented which verify the proposed control principle and demonstrate the practicality of the circuit topology.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.639-642
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• 1999

An integrated zero current switching(ZCS) quasi-resonant converter(QRC) for power factor correction and high efficiency with single switch is proposed in this thesis. Boost integrated circuit operating discontinuous conduction mode(DCM) and QRC are used for power factor correction and reducing switching loss, respectively. A prototype converter has been designed and experimented. At rated condition, the THD in the input current waveform of this prototype has approximately 18%. The efficiency is obtained about 70%, the power factor is about 0.985 as well. Therefore, the proposed converter is suitable for a low power level converter with operating switching frequency above several hundred KHz.

• Journal of Communications and Networks
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• v.8 no.4
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• pp.378-390
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• 2006

Many distributed applications build overlays on top of the Internet. Several unsolved issues at the network layer can explain this trend to implement network services such as multicast, mobility, and security at the application layer. On one hand, overlays creating basic topologies are usually limited in flexibility and scalability. On the other hand, overlays creating complex topologies require some form of application level addressing, routing, and naming mechanisms. Our aim is to design an efficient and robust addressing, routing, and naming infrastructure for these complex overlays. Our only assumption is that they are deployed over the Internet topology. Applications that use our middleware will be relieved from managing their own overlay topologies. Our infrastructure is based on the separation of the naming and the addressing planes and provides a convergence plane for the current heterogeneous Internet environment. To implement this property, we have designed a scalable distributed k-resilient name to address binding system. This paper describes the design of our overlay infrastructure and presents performance results concerning its routing scalability, its path inflation efficiency and its resilience to network dynamics.