• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.557-560
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• 2005

The purpose of this study is to realize DHCP server based on embedded system. To achieve this, embedded Linux was ported in ez Bord-M01 mounted with Intel Strong ARM SA1110 processor, and ethernet-based network was constructed for network function. In this way, this study suggests embedded DHCP server where Window and Linux client hosts are dynamically configurated as network information by dynamically assigning network information in embedded board.

• Journal of IKEEE
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• v.24 no.4
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• pp.1172-1175
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• 2020

Automotive ECU integrates CPU core, IVN controller, memory interface, sensor interface, I/O interface, and so on. Current automotive ECUs are often developed with proprietary processor architectures. However, demends for standard processors such as ARM and RISC-V increase rapidly for saftware compatibility in autonomous vehicles and connected cars. In this paper, an automotive ECU is designed for parking assist system based on RISC-V with open instruction set architecture. It includes 32b RISC-V CPU core, IVN controllers such as CAN and LIN, memory interfaces such as ROM and SRAM, and I/O interfaces such as SPI, UART, and I2C. Fabricated in 65nm CMOS technology, its operating frequency, area, and gate count are 50MHz, 0.37㎟, and 55,310 gates, respectively.

• Journal of IKEEE
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• v.18 no.4
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• pp.471-477
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• 2014

In this paper, we propose a low-cost license plate recognition system based on smart cam system using Android. The proposed system consists of a portable device and server. Potable device Hardware consists of ARM Cortex-A9 (S5PV210) processor control unit, a power supply device, wired and wireless communication, input/output unit. We develope Linux kernel and dedicated device driver for WiFi module and camera. The license plate recognition algorithm is consisted of setting candidate plates areas with canny edge detector, extracting license plate number with Labeling, recognizing with template matching, etc. The number that is recognized by the device is transmitted to the remote server via the user mobile phone, and the server re-transfer the vehicle information in the database to the portable device. To verify the utility of the proposed system, user photographs the license plate of any vehicle in the natural environment. Confirming the recognition result, the recognition rate was 95%. The proposed system was suitable for low cost portable license plate recognition device, it enabled the stability of the system when used long time by using the Android operating system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.3
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• pp.301-306
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• 2003

We have designed embedded web server system and ported Linux operating system version 2.4.1 at our system. And then We implemented to control and monitor widely separated hardware. Web server is the Boa web server with General Public License. We designed for this system using of Cirrus logic's EP7312 ARM core base processor and connecting input and output device at GPIO port of EP7312. Device driver of General purpose I/O for Linux OS is designed. And then the application program controlling driver is implemented to use of common gate interface C language. User is available to control and monitor at client PC. This method have benefit to reduce the Expenditure of hardware design and development time against PC base system and have various and capacious application against firmware base system.

• Proceedings of the Korea Contents Association Conference
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• 2009.05a
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• pp.17-22
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• 2009

DaVinci processors are popular media processors for implementing embedded multimedia applications. They support dual core architecture: ARM9 core for video I/O handling as well as system management and peripheral handling, and DSP C64+ core for effective digital signal processing. In this paper, we propose our efforts for optimal implementation of object tracking algorithm in DaVinci-based smart camera which is being designed and implemented by our laboratory. The smart camera in this paper is supposed to support object detection, object tracking, object classification and detection of intrusion into surveillance regions and sending the detection event to remote clients using IP protocol. Object tracking algorithm is computationally expensive since it needs to process several procedures such as foreground mask extraction, foreground mask correction, connected component labeling, blob region calculation, object prediction, and etc. which require large amount of computation times. Thus, if it is not implemented optimally in Davinci-based processors, one cannot expect real-time performance of the smart camera.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.6
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• pp.1011-1018
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• 2006

Due to rapid development of mobile communication terminals and various requests of their users, multimedia information including image information has been the basis of mobile communication contents. In order to use vectored image information efficiently, which is more favorable than bit-mapped image information when transmission delay time and costs are considered, efficient vector graphics supporting systems are needed. Therefore, vector graphics kernel systems have been proposed and standardization attempts have been made in order to increase interoperability. In this paper, a vector graphics kernel based on OpenVG is designed and implemented. OpenVG was proposed as a standard vector graphics kernel by Khronos Group recently. The implemented vector graphics kernel, named by alexVG, is developed on a PC emulator as well as on a development board equipped with an ARM processor. In addition, performance tests are made in order to verify its functions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.51-58
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• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.43-51
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• 2008

In this paper, we are implemented low-power structure for Inter prediction, Intra prediction, Deblocking filter, Transform and Quantization blocks in H.264/AVC Encoder. The proposed Inter/Intra prediction blocks are shown 60.2% cell area reduction by adder reduction through Distributed Arithmetic, 44.3% add operation reduction using MUX for hardware share in Deblocking filter block. Furthermore we applied CSD and CSS process to reduce the cell area instead of multipliers that take a lot of area. The FPGA(Field Programmable Gate Array) and ARM Process based H.264/AVC encoder is implemented using proposed low power IPs. The proposed structure Platforms are implemented to interlock with FPGA and ARM processors. H.264/AVC Encoder implementation using Platforms shows that proposed low-power IPs can use H.264/AVC Encoder SoC effectively.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.4
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• pp.233-239
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• 2015

This paper describes a method that is integrated trace for real-time virtualization environment. This method has solved the problem that the performance trace may not be able to analyze integrated method between heterogeneous operating systems which is consists of real-time operating systems and general-purpose operating system. In order to solve this problem, we have attempted to reuse the performance analysis function in general-purpose operating system, thereby real-time operating systems can be analyzed along with general-operating system. Furthermore, we have implemented a prototype based on ARM Cortex-A15 dual-core processor. By using this integrated trace method, real-time system developers can be improved productivity and reliability of results on real-time virtualization environment.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.735-738
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• 2005

This paper presents an AMBA-based IP that can perform the deblocking filtering operations required in the H.264 video compression. The deblocking filter circuit was optimized for area and performance. The AHB wrapper was added to the circuit to interface with the AMBA-based platform. The AMBA-compliant operation of the proposed IP was verified on the platform board with Xilinx Virtex2 XC2V600 FPGA and ARM9 processor.