• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1541-1550
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• 2004

In this paper, we propose an advanced hardware architecture for fast multi-resolution motion estimation of the video coding standard MPEG-1,2 and MPEG-4 AVC. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and fast operation by using the shared memory, the special ram architecture, the motion vector for 4 pixel x 4 pixel, the spiral search and so on. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur Altera FPGA and also by ASIC synthesis using Samsung 0.18 m CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 140 MHz, processing more than 1,100 QCIF video frames or 70 4CIF video frames per second. The hardware is going to be used as a core module when implementing a complete MPEG-4 AVC video encoder ASIC for real-time multimedia application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.51-58
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• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design

• Biomolecules & Therapeutics
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• v.18 no.2
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• pp.219-225
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• 2010

We tested whether ginsenosides $Rg_3$-standardized ginseng extract (RGE) has anti-stress effects in restraint-stressed animals. RGE increased time spent in the open arms and open arm entries in the elevated plus-maze test. In addition, RGE blocked the reduction of center zone distance and stereotypes behaviors in the open-field test. RGE also increased head dips in stressed mice, indicating anxiolytic-like effects. Stress decreased movement distance and duration, burrowing, and rearing frequency but increased face washing and grooming. RGE significantly reversed burrowing and rearing activity in stressed mice. In addition, we measured sleep architecture in restraint stressed rats using EEG recorder. Stress increased rapid eye movement (REM) sleep, but total sleep and non-rapid eye movement (NREM) sleep were not changed. RGE did not affect sleep architecture in stressed rats. These behavioral experiments suggest that RGE has anti-stress effects in restraint-stressed animal models.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.94-97
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• 2002

A VLSI architecture of an Ogg Vorbis decoder is proposed : which is dedicated to portable audio appliances. Referring to the computational cost analysis of the decoding processes, the LSP (Line Spectrum Pair) process, which takes more than 50% of the total processing time, can be regarded as a bottleneck to achieve realtime processing by embedded Processors. Thus in our decoder a specific hardware architecture is devised for the LSP process so as to be integrated into a single chip together with an ARM7TDMI processor. In addition, in order to reduce the total hardware cost, instead of the floating point arithmetic, the fixed point arithmetic is adopted. The LSP module has been implemented with 9,740 gates by using a Virtual Silicon 0.l5$\mu\textrm{m}$ CMOS technology, which operates at 58.8MHz with the total CPU load reduced by 57%. It is also verified that the use of the fixed point arithmetic does not incur any significant sound distortion.

• Journal of the Korea Society of Computer and Information
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• v.18 no.7
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• pp.1-10
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• 2013

In this paper, the parallel branch instruction is proposed which executes a branch instruction and the frequently used instruction simultaneously to improve the performance of Thumb-2 instruction set architecture. In the proposed approach, new 32-bit parallel branch instructions are introduced which combine 16-bit branch instruction with each of the frequently used 16-bit LOAD, ADD, MOV, STORE, and SUB instructions, respectively. To provide the encoding space of the new instructions, the register field in less frequently executed instructions is reduced, and the new instructions are encoded by using the saved bits. Experiments show that the proposed approach improves performance by an average of 8.0% when compared to the conventional approach.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.74-79
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• 2007

In general, the high cost, long time, and complex steps are required in the design and implementation of MPSoC(Multi-Processor System on a Chip), therefore a platform is used to test the functionality and performance of IPs(Intellectual Properties). In this paper, we study a platform architecture to verify IPs based on Interconnect Network among processors, and show that the MPSoC platform gives better performance than a single processor for an application program.

• Journal of the Society of Naval Architects of Korea
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• v.52 no.3
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• pp.187-197
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• 2015

This study aims the development of a semi-analytic method for the parametric roll of large containerships advancing in longitudinal waves. A 1.5 Degree-of-Freedom(DOF) model is proposed to account the change of transverse stability induced by wave elevations and vertical motions (heave and pitch). By approximating the nonlinearity of restoring moment at large heel angles, the magnitude of roll amplitude is predicted as well as susceptibility check for parametric roll occurrence. In order to increase the accuracy of the prediction, the relationship between righting arm(GZ) and metacentric height(GM) is examined in the presence of incident waves, and then a new formula is proposed. Based on the linear approximation of the mean and first harmonic component of GM, the equation of parametric roll in irregular wave excitations is introduced, and the computational results of the proposed model are validated by comparing those of weakly nonlinear simulation based on an impulse-response-function method combined with strip theory. The present semi-analytic doesn’ t require heavy computational effort, so that it is very efficient particularly when numerous sea conditions for the analysis of parametric roll should be considered.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.229-236
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• 2005

This paper presents a system level architecture evaluation technique that leverages transaction level modeling but also significantly extends it to the realm of system level performance evaluation. A major issue lies with the modeling effort. To reduce the modeling effort the proposed technique develops the concept of worst case scenarios. Since the memory controller is often found to be an important component that critically affects the system performance and thus needs optimization, the paper further addresses how to evaluate and optimize the memory controllers, focusing on the test environment and the methodology. The paper also presents an industrial case study using a real state-of-the-art design. In the case study, it is reported that the proposed technique has helped successfully find the performance bottleneck and provide appropriate feedback on time.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.65-70
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• 2015

In this paper, we describe the world's first real-time ray-tracing chip architecture. Ray-tracing technology generates high-quality 3D graphics images better than current rasterization technology by providing four essential light effects: shadow, reflection, refraction and transmission. The real-time ray-tracing chip named RayChip includes a real-time ray-tracing graphics processing unit and an accelerating tree-building unit. An ARM Ltd. central processing unit (CPU) and other peripherals are also included to support all processes of 3D graphics applications. Using the accelerating tree-building unit named RayTree to minimize the CPU load, the chip uses a low-end CPU and decreases both silicon area and power consumption. The evaluation results with RayChip show appropriate performance to support real-time ray tracing in high-definition (HD) resolution, while the rendered images are scaled to full HD resolution. The chip also integrates the Linux operating system and the familiar OpenGL for Embedded Systems application programming interface for easy application development.

• International journal of steel structures
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• v.18 no.5
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• pp.1741-1753
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• 2018

Metallic dampers are sacrificial devices (fuses) that dissipate significant energy during earthquakes while protecting other parts of structures from possible damage. In addition to numerous implementation opportunities of other base isolation systems, U-shaped dampers (UD) are one of the widely investigated and used devices in practice especially in Japan. The present study focuses on enhancing seismic performance of these types of dampers by changing their geometric properties. UDs with perforated (i.e. with holes) and/or nonparallel arms are developed for this purpose. For a better comparison, the criterion of equal material volume (or mass) has been utilized. Three dimensional finite element models of the new type of UDs are formed and investigated numerically under selected displacement histories. Based on the obtained hysteretic curves; dissipated energy intensities, effective stiffness ratios, reaction forces, effective damping ratios are evaluated in this parametric study. It is found that both damper types have merits in use of seismic applications and that the selection of the damper configuration is dependent on the design specific issues.