• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.849-852
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• 2001

본 눈문에서는 뒤틀림, 응력, 압력[1], 토크, 가속도 등의 물리적인 동적 현상을 측정하여 수집된 데이터를 처리하기 위한 신호처리(Signal Processins) 기능이 결합되어 넓은 용도로 활용할 수 있는 센서 신호 수집 시스템을 구현하였다. 구현된 시스템은 data acquisition board 의 하드웨어와 소프트웨어로 나누어 볼 수 있다. 하드웨어의 구성은 아날로그부, 디지털부, 그리고 시스템 인터페이스 처리부로 되어 있다. 아날로그부에서는 센서신호를 받아서, PGA (Programmable Gain Amplifier)[2]와 Op-Amp를 사용하여 signal conditioning 처리하여 8차 Lowpass Filter 로 보낸다. Filtering 된 신호는 ADC (Analog to Digital Converter) 가 내장되어 있는 PIC(3) microcontroller로 보내져 AD변환과 디지털 신호 처리를 한다. 처리된 신호는 RS232 인터페이스를 통해 호스트 컴퓨터로 보내 사용자가 분석할 수 있도록 한다. 또한 LCD display 실시간으로 확인, 분석할 수 있으며 동시에analog output에서 센서신호의 특징을 분석 할 수 있도록 한다.

• Journal of the Korean Institute of Navigation
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• v.19 no.3
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• pp.29-34
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• 1995

IEC and CISPR have continuously endeavored the measurement method of Immunity Test as international unification, but not established yet. The main reason is that the measurement method and the normalization of threshold to obtain the complicated parameters for Immunity Test are difficult. Thus, the Immunity Test Setups are used differently according to the measured electromagnetic environments. This study developed an Immunity Test System and Algorithm for measurement software suitable for IEC801-3 Regulatons using ready-made amplifier, signal generator, and developes interconnecting interface board interacting with other appratus i.e., RF Switch, Power Meter, Field Sensor and Pre-amp. We are to develope an automated software using Top/Down and OOP(Object Oriented Programming) method.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.606-608
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• 2006

This paper describes a 8bit 10MS/s low power pipelined analog-to-digital converter(ADC). To reduce power consumption in proposed ADC, a high gain op-amp that consumes large power in MDAC(multiplying DAC) of conventional pipelined ADC is replaced with simple comparator and current sources. Moreover, differential charge transfer amplifier technique with latch in the sub-ADC reduces the power consumption to less than half compared with the conventional sub-ADC which use high speed comparator. The proposed ADC shows the power consumption of 1.8mW at supply voltage of 1.8V. This proposed ADC is suitable to apply to the portable display device. The circuit was implemented with 0.18um CMOS technology and the core size of circuit is 2.5mm${\times}$1mm.

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.189-196
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• 2015

In this paper, we present a rotating auto-zeroing offset cancellation technique, which can improve the performance of touch screen sensing circuits. Our target touch screen detection method employs multiple continuous sine waves to achieve a high speed for large touch screens. While conventional auto-zeroing schemes cannot handle such continuous signals properly, the proposed scheme does not suffer from switching noise and provides effective offset cancellation for continuous signals. Experimental results show that the proposed technique improves the signal-to-noise ratio by 14 dB compared to a conventional offset cancellation scheme. For the realistic simulation results, we used Cadence SPECTRE with an accurate TSP model and noise source. We also applied an asymmetric device size (10% MOS size mismatch) to the OP Amp design in order to measure the effectiveness of offset cancellation. We implemented the proposed circuit as part of a touch screen controller system-on-chip by using a Magnachip/SK Hynix 0.18-µm complementary metal-oxide semiconductor (CMOS) process.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.686-689
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• 2003

This paper describes two kind of new concept for low power consumption for small area TFT-LCDs. First, the proposed analog buffer could reduce the static current by adopting new scheme. Second, new data driver structure reduced DC power consumption by reducing the number of operational amplifier (op-amp). As simulation results of Hspice, the quiescent current of proposed analog buffer is less than $0.8{\mu}A$ and the DC power consumption is reduced about $40{\sim}50%$ compared with conventional ones.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.817-824
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• 2016

A simultaneous bidirectional transceiver over a single wire has been developed in a 65 nm CMOS technology for a command and control bus. The echo signals of the simultaneous bidirectional link are cancelled by controlling the decision level of receiver comparators without power-hungry operational amplifier (op-amp) based circuits. With the clock information embedded in the rising edges of the signals sent from the source side to the sink side, the data is recovered by an open-loop digital circuit with 20 times blind oversampling. The data rate of the simultaneous bidirectional transceiver in each direction is 75 Mbps and therefore the overall signaling bandwidth is 150 Mbps. The measured energy efficiency of the transceiver is 56.7 pJ/b and the bit-error-rate (BER) is less than $10^{-12}$ with $2^7-1$ pseudo-random binary sequence (PRBS) pattern for both signaling directions.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.307-307
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• 2010

ICRF 또는 NB 시스템에 의해 가열된 고에너지 이온들을 측정하는 것은 핵융합 플라즈마에서 중요한 과제 중의 하나이다. 특히 ICRF를 이용한 D(H) 플라즈마의 H minority의 가열은 H의 분율에 따라 가열의 정도가 달라지고 이 결과는 이온의 고에너지 측정을 통해서 확인할 수 있으므로 정확한 고속 이온의 측정은 매우 중요하다. 본 연구에서는 고속 이온을 전하 교환된 중성입자로부터 측정하는 중성입자 검출기를 개발하였다. Si 광다이오드인 AXUV3ELA를 기반으로 50-300 keV 범위의 고에너지 H 및 D 이온을 측정할 수 있는 소형의 중성입자 검출기(Compact Neutral Particle Analyzer : CNPA)가 설계 제작되었다. 검출된 신호는 Pre-amp와 shaping amplifier를 통해 증폭되고 shaping 되며 마지막으로 다중채널 분석기(Multi Channel Analyzer : MCA)를 통해서 계수된다. 본 발표에서는 NPA의 구체적인 설계 특성과 함께 Am-241 gamma ray 선원을 이용한 NPA의 시험 및 보정결과를 보고할 예정이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.9 no.1
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• pp.25-29
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• 1984

The active compensation of operational amplifeir is that it compensates the phase shift and the attennation of gain of OP Amp, according as the frequency increases. The compensation circuit is applied to VCVS and interting integrator. For VCVS, the phase shift of proposed compensated circuit is not concern with the frequency and the gain chracteristic is better than the proposde circuit by Soliman, according as the rate of feedback resistors of compensated circuit changes. Voltage follower accomplishies compgnsation using the same circuit. Also, the compensation circuit to increase O-ffactor in inverting integrator is proposed.

• Journal of Institute of Control, Robotics and Systems
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• v.12 no.9
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• pp.912-917
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• 2006

A strain gauge weight measuring instrumentation system was designed with RF sensor network facilities. In the sensor module system data conversion and a series of signal processing were totally equipped. 16 strain gauges are incoming sensors and each output of the strain gauge was amplified and filtered for proper analog signal processing. Several measuring instrumentation OP amps and general purposed OP amps were used. 12 bits A/D converters converted analog signals to digital bits and a PIC microprocessor controlled the 16 channels of strain gauges. RF RS232 modules were used for wireless communication between the PIC microprocessor and an Ethernet host far a remote sensor monitoring system development.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.154-158
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• 2005

In this paper, we design optical receiver composed of CDR(clock and data recovery), SA(sense amp), TIA(transimpe dence amplifier), and decision circuit. The optical receiver can be classified to two main block, one is Deserializer composed of CDR and SA, another is PD receiver composed of preamplifier(샴), peak detector, etc. In this paper, we propose CDR using delayed data topology that could improve defects of existing CDR. The optical receiver that is proposed in this paper has the role of translation a 1.25 Gb/s optical signal to $10{\times}125 Mb/s$ array electric signals. This optical receiver is verified by simulator(hspice) using 0.35 um CMOS technology.