• ETRI Journal
• /
• v.29 no.2
• /
• pp.212-218
• /
• 2007

A novel low-voltage CMOS current feedback operational amplifier (CFOA) is presented. This realization nearly allows rail-to-rail input/output operations. Also, it provides high driving current capabilities. The CFOA operates at supply voltages of ${\pm}0.75V$ with a total standby current of 304 ${\mu}A$. The circuit exhibits a bandwidth better than 120 MHz and a current drive capability of ${\pm}1$ mA. An application of the CFOA to realize a new all-pass filter is given. PSpice simulation results using 0.25 ${\mu}m$ CMOS technology parameters for the proposed CFOA and its application are given.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.1
• /
• pp.100-105
• /
• 2003

In this paper, we propose the novel test method effectively to detect short and open faults in CMOS op-amp. The proposed method uses a sinusoidal signal with higher frequency than unit gain bandwidth. Since the proposed test method doesn't need complex algorithm to generate test pattern, the time of test pattern generation is short, and test cost is reduced because a single test pattern is able to detect all target faults. To verify the proposed method, CMOS two-stage operational amplifier with short and open faults is designed and the simulation results of HSPICE for the circuit have shown that the proposed test method can detect short and open faults in CMOS op-amp.

• Korean Journal of Optics and Photonics
• /
• v.10 no.5
• /
• pp.424-429
• /
• 1999

The amplifier properties of single distributed feedback dye laser with 106 ps pulse width and 616 nm wavelength were invested using only one XeCl-excimer laser as pump source. For optimized amplification of DFDL, the three-stage amplifiers were arranged with increasing cross-section and accordingly increasing pump energies. The first AmpI, II stages were dye cell of 5 mm, 10 mm and contained a $6{\times}10^{-4}$ [mol/l](solvent : Methanol) of Rhodamine 610. Double-pass amplification in the AmPII was measured to suppress the ASE by using a diffraction grating. The beam intensity of AmpI, II was saturated with a gain of respectively 10 and 48. The last AmpIII was Bethune cell of 30 mm and contained a $3{\times}10^ {-4}$ [mol/l] (solvent : Ethanol) of Rhodamine 610. In the single-pass and double-pass amplification, the output energy was obtained 168.2 $\mu$J and 471$\mu$J respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.6
• /
• pp.641-647
• /
• 2011

This paper describes a design and fabrication of SDLVA. The SDLVA operates 0.5~2.0 GHz with -70~0 dBm dynamic range. The SDLVA is consisted of 5-stage RF block, 2-stage detector block and summation circuit using clamping op-amp to improve video linearity. The result of measure, SDLVA of RF path has over 73 dB small-signal gain and 10.1~12.2 dBm saturation power. The video path has 25 mV/ dB${\pm}$1.0 mV and under ${\pm}$1.5 dB video linearity.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2013.10a
• /
• pp.726-729
• /
• 2013

In this paper, low power and high slew rate CMOS rail to rail input/output opamp applicable for ouput buffer amp, in LCD source driver IC, is proposed. Proposed op-amp, is realized the characteristics of low power consumption and high slew rate adding the newly designed control stage of class-B to the conventional output stage of class-AB. From the simulation results, we know that the proposed opamp buffer can drive a 1000pF capacitive load with a 6.5V/us slew-rate, while drawing only the the power consumption of 1.19mW from 3.3V power supply.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.5
• /
• pp.579-587
• /
• 2014

This paper presents a variable gain amplifier (VGA) for an analog front-end (AFE) of ultrasound medical imaging. This VGA has a closed-loop topology and shows a 37-dB-linear characteristic with a single-stage amplifier. It consists of an op-amp, a non-binary-weighted capacitor array, and a gain-control block. This non-binary-weighted capacitor array reduces the required number of capacitors and the complexity of the gain-control block. The VGA has been fabricated in a 0.35-mm CMOS process. This work gives the largest gain range of 37 dB per stage, the largest P1 dB of 9.5 dBm at the 3.3-V among the recent VGA circuits available in the literature. The voltage gain is controlled in the range of [-10, 27] dB in a linear-in-dB scale with 16 steps by a 4-bit digital code. The VGA has a bandpass characteristic with a passband of [20 kHz, 8 MHz].

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.2
• /
• pp.16-21
• /
• 1993

A newly advanced method of characterizing large signal S-parameters of TR using the overall gain of normally operating TR is proposed based on the load pull method which gives the matching network only. Large signal S-parameters of TR are characterized from the circuit which consists of TR and 3dB Coupler Tuners at the input and output ports, and which is B class biased with 0dBminput signal. Amplifier can be designed to have 8.5dB gain at 770MHz using the calculated large signal S-parameters with the resulting gain of 8.786dB.

• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 2000.12a
• /
• pp.237-240
• /
• 2000

본 논문에서는 ISM(Industrial Scientific Medical) 대역 424MHz부터 429MHz까지의 범위에서 동작하는 열차 후부 감시제어 시스템용 RF 전력증폭기를 설계 및 제작하였다. 424MHz대역에서의 2W급 대전력 증폭기의 설계방법으로는 Double Stub Tuner구조를 이용하여 최적 부하 임피던스를 추출하는 방법을 제시하였고, 초고주파 시뮬레이터인 Serenade8.0을 사용하여 Drive_amp와 LPF를 설계하였다. 제작된 Drive_amp와 LPF의 성능 및 특성은 시뮬레이션 한 결과와 거의 일치하였으며, 대전력 증폭기의 측정결과로는 추출하고자 하는 출력 레벨인 33㏈m을 얻을 누 있었고, 원신호의 Hamonic 주파수 성분과는 40.34㏈c의 결과를 보임으로써 안정된 전력증폭기를 구현하였다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.1
• /
• pp.20-27
• /
• 2007

An analytic design guide was formulated for the design of 3-stage CMOS OP amp with the nested Gm-C(NGCC) frequency compensation. The proposed design guide generates straight-forwardly the design parameters such as the W/L ratio and current of each transistor from the given design specifications, such as, gain-bandwidth, phase margin, the ratio of compensation capacitance to load capacitance. The applications of this design guide to the two cases of 10pF and 100pF load capacitances, shows that the designed OP amp work with a reasonable performance in both cases, for the range of compensation capacitance from 10% to 100% of load capacitance.

• Proceedings of the IEEK Conference
• /
• 2007.07a
• /
• pp.341-342
• /
• 2007

The IRFPA (InfraRed Focal Plane Array) ROIC (ReadOut Integrated Circuit) was designed in folded-cascode Op-Amp using $0.35{\mu}m$ CMOS technology. As the folded-cascode has high open-loop voltage gain and fast settling time, that used in many analog circuit designs. In this paper, folded-cascode Op-Amp for ROIC of the $32{\times}32$ IRFPA has been designed. HSPICE simulation results are unit gain bandwidth of 13.0MHz, 90.6 dB open loop gain, 8 V/${\mu}m$ slew rate, 600 ns settling time and $66^{\circ}$ phase margin.