• Korean Journal of Materials Research
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• v.6 no.7
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• pp.700-708
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• 1996

Electroless plating technique was utilized to flip chip bonding to improve surface mount characteristics. Each step of plating procedure was studied in terms pf pH, plating temperature and plating time. Al patterned 4 inch Si wafers were used as substrstes and zincate was used as an activation solution. Heat treatment was carried out for all the specimens in the temperature range from room temperature to $400^{\circ}C$ for $30^{\circ}C$ minutes in a vacuum furnace. Homogeneous distribution of Zn particles of size was obtained by the zincate treatment with pH 13 ~ 13.5, solution concentration of 15 ~ 25% at room temperature. The plating rates for both Ni-P and Au electroless plating steps increased with increasing the plating temperature and pH. The main crystallization planes of the plated Au were found to be (111) a pH 7 and (200) and (111) at pH 9 independent of the annealing temperature.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.139-142
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• 2008

An X-band MMIC power amplifier for radar application is developed using $0.25-{\mu}m$ gate length GaAs pHEMT technology. A bus-bar power combiner at output stage is used to minimize the combiner size and to simplify bias network. The fabricated power amplifier shows 38.75 dBm (7.5 Watt) Psat at 10 GHz. The chip size is $3.5\;mm{\times}3.9\;mm$.

• Electronics and Telecommunications Trends
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• v.35 no.3
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• pp.76-84
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• 2020

Neuromorphic hardware refers to brain-inspired computers or components that model an artificial neural network comprising densely connected parallel neurons and synapses. The major element in the widespread deployment of neural networks in embedded devices are efficient architecture for neuromorphic hardware with regard to performance, power consumption, and chip area. Spiking neural networks (SiNNs) are brain-inspired in which the communication among neurons is modeled in the form of spikes. Owing to brainlike operating modes, SNNs can be power efficient. However, issues still exist with research and actual application of SNNs. In this issue, we focus on the technology development cases and market trends of two typical tracks, which are listed above, from the point of view of artificial intelligence neuromorphic circuits and subsequently describe their future development prospects.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1722-1723
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• 2011

LED는 광학적 특성을 유지하기 위해서는 방열설계가 매우 중요한 문제로 요구된다. 대부분의 반도체 소자의 고장 원인은 85%정도가 열로 인한 것이며 고출력 LED의 인가된 에너지는 20%정도가 광으로 출력되며 나머지 80%정도가 열로 전환된다. 이러한 이유 때문에 LED소자의 신뢰성과 효율 향상을 위한 방열성능의 극대화가 필요하다. 본 연구에서는 AI MCPCB 기판에 기반을 둔 COB Type의 고출력 LED모듈의 구조를 제안 하였으며, LED Chip과 금속base 사이의 절연층 유무의 관점에서의 비교 열 시뮬레이션을 통해 결과를 분석하여 고출력 COB LED모듈의 방열 특성을 최적화 하였다.

• Journal of Navigation and Port Research
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• v.33 no.10
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• pp.685-690
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• 2009

International Maritime Organization (IMO) recommends the installation of an Automatic Identification System (AIS) according to requirements by SOLAS to avoid maritime collision. AIS provides traffic information of other ships that may be used for maritime traffic control, SAR (Search and Rescue) and collision avoidance to apply safety management. In this paper, preliminary results to implement an aeronautical surveillance transceiver using AIS transceiver based on ADS-B concepts are described. Although altitude information is not required for AIS since the AIS is operated at MSL (Mean Sea Level), altitude information can be extracted by a GPS (Global Positioning System) chip-set in the AIS transceiver. ADS-B transceiver is implemented by defining a surveillance message format including the altitude information and modifying SOTDMA (Self-Organizing Time Division Multiple Access) protocol. Ground tests and flight tests are performed to validate the implementation results.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2009.06a
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• pp.19-20
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• 2009

International Maritime Organization(IMO) recommends the installation of an Automatic Identification System(AIS) according to requirements by SOLAS Chapter 5 to avoid maritime collision. AIS provides traffic information of other ships that may be used for maritime traffic control, SAR(Search and Rescue) and collision avoidance to apply safety management. In this paper, preliminary results to implement an aeronautical surveillance transceiver using AIS transceiver based on ADS-B concepts are described. Although altitude information is not required for AIS since the AIS is operated at MSL(Mean Sea Level), altitude information can be extracted by a GPS chip-set in the ALS transceiver. ADS-B transceiver is implemented by defining a surveillance message format including the altitude information and modifying SOTDMA protocol. Ground tests and flight tests are performed to validate the implementation results.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.5
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• pp.891-898
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• 2022

Along with global interest, drones are expanding the base of utilization such as transportation of goods, forest protection, and safety management, and cluster flights are being applied in various fields such as military operations and environmental monitoring. Currently, specialized networks such as e-UM 5G for services in specific industries are being established in Korea. In this regard, drone systems are also moving to establish specialized networks to provide services that are fused with AI and autonomous flight. As drones converge with various services, various security threats in various environments are also subordinated, and in response, requirements and guidelines for drone security are being prepared in Korea. In this paper, we propose a technology method for peer identification and safe information provision between cluster flight drones by utilizing a cryptographic module equipped with wireless LAN and quantum entropy-based random number generator in a cluster flight system and a mobile communication network such as e-UM 5G.

• Journal of Life Science
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• v.34 no.5
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• pp.339-355
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• 2024

The pulmonary system is a highly complex system that can only be understood by integrating its functional and structural aspects. Hence, in vivo animal models are generally used for pathological studies of pulmonary diseases and the evaluation of inhalation toxicity. However, to reduce the number of animals used in experimentation and with the consideration of animal welfare, alternative methods have been extensively developed. Notably, the Organization for Economic Co-operation and Development (OECD) and the United States Environmental Protection Agency (USEPA) have agreed to prohibit animal testing after 2030. Therefore, the latest advances in biotechnology are revolutionizing the approach to developing in vitro inhalation models. For example, lung organ-on-a-chip (OoC) and organoid models have been intensively studied alongside advancements in three-dimensional (3D) bioprinting and microfluidic systems. These modeling systems can more precisely imitate the complex biological environment compared to traditional in vivo animal experiments. This review paper addresses multiple aspects of the recent in vitro modeling systems of lung OoC and organoids. It includes discussions on the use of endothelial cells, epithelial cells, and fibroblasts composed of lung alveoli generated from pluripotent stem cells or cancer cells. Moreover, it covers lung air-liquid interface (ALI) systems, transwell membrane materials, and in silico models using artificial intelligence (AI) for the establishment and evaluation of in vitro pulmonary systems.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.102-102
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• 2018

Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.51-56
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• 2010

In this paper, a novel Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF. The size of chip is $255{\mu}m$ $\times$ $935.5{\mu}m$ including the LF. The proposed P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.