• Proceedings of the Korea Multimedia Society Conference
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• 2002.05d
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• pp.920-925
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• 2002

급속히 고갈되어가는 IPv4의 주소 부족 문제를 해결하기 위하여, 차세대 인터넷 프로토콜 (IP)인 IPv6가 제안되었고 실용화 단계까지 진행되고 있다. IPv6에서의 요구 사항 중의 하나인 IPSec은 IPv4의 취약한 보안 기능을 강화하는 것이다. 현재 IPSec에서 반드시 구현되어야 할 암호화 알고리즘으로 MD5, SHA1, 3DES와 더불어 최근 표준안으로 채택된 AES(Rijndael)을 요구하고 있다. IPv6의 고속 수행을 위하여는 IPSec이 하드웨어로 구현될 필요성이 있으므로, 본 논문에서는 IPv6용 IPSec 칩에 탑재할 AES 하드웨어 모듈을 구현하였다. 제안된 하드웨어 모듈은 효율적인 알고리즘의 수행과 구현을 위하여, 암호화/복호화 단계가 동일한 구조로 동작하도록 설계하였으며, 가변적인 128, 196,256 비트의 키에 대하여 같은 로직을 사용하도록 설계하였다.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.3
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• pp.121-127
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• 2012

An integrated crypto engine for encryption and decryption of AES algorithm based on unified data-path architecture is efficiently designed and implemented in this paper. In order to unify the design of encryption and decryption, internal steps in single round is adjusted so as to operate with columns after row operation is completed and efficient method for a buffer is developed to simplify the Shift Rows operation. Also, only one S-box is used for both key expansion and crypto operation and Key-Box saving expended key is introduced provide the key required in encryption and decryption. The functional simulation based on ModelSim simulator shows that 164 clocks are required to process the data of 128bits in the proposed engine. In addition, the proposed engine is implemented with 6,801 gates by using Xilinx Synthesizer. This demonstrate that 40% gates savings is achieved in the proposed engine, compared to individual designs of encryption and decryption engine.

• Proceedings of the Korea Information Processing Society Conference
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• 2017.11a
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• pp.182-185
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• 2017

넌어드레스(Non-Addressable) 장비는 IP 주소를 포함한 기타 어느 계정을 갖지 않는 통신 보안 장비로서, 해킹을 포함한 허가되지 않은 공격들로부터 원천적으로 단말을 보안할 수 있다. 본 논문에서는 넌어드레스 장비에서 AES 방식으로 데이터를 암/복호화 시 성능을 향상시키기 위한 방법을 제시한다. AES-128, 192, 256에서의 암/복호화 시간, CPU 사용량, 메모리 사용량, 실제 데이터의 전송속도를 비교하여 최선의 설정 방법을 도출한다.

• Journal of KIISE
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• v.44 no.6
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• pp.637-642
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• 2017

Honey Encryption (HE) is a technique to overcome the weakness of a brute-force attack of the existing password-based encryption (PBE). By outputting a plausible plaintext even if the wrong key is entered, it provides message recovery security which an attacker can tolerate even if the attacker tries a brute-force attack against a small entropy secret key. However, application of a cipher that requires encryption padding to the HE present a bigger problem than the conventional PBE method. In this paper, we apply a typical block cipher (AES-128) and a stream cipher (A5 / 1) to verify the problem of padding through the analysis of the sentence frequency and we propose a safe operation method of the HE.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.11
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• pp.972-981
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• 2013

Future aspects of the has turned into a network centric warfare(NCW). Organically combined wired and wireless networks in a variety of cross-of-the-art combat power factor utilization of information and communication technology is a key element of NCW implementation. At used various information in the NCW must be the confidentiality and integrity excellent then quick situation assessment through reliability the real-time processing, which is the core of winning the war. In this paper, NCW is one of the key technologies of the implementation of 128-bit output stream cipher algorithm is proposed. AES-based stream cipher developed by applying modified OFB mode the confidentiality and integrity as well as hardware implementation to the security and real-time processing is superior.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2016.06a
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• pp.220-221
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• 2016

최근 UHD 방송서비스에 대한 관심이 고조됨에 따라 고품질 방송 콘텐츠 보호에 대한 요구가 증가하고 있다. 이에 따라, DVB, MPEG, ATSC 등 국제 표준단체에서는 기존 방식보다 보안 성능이 우수한 디지털 방송 보호 규격을 논의하고 있으며, 디즈니, 파라마운트, 소니 픽처스 등 세계 주요 콘텐츠 제작사들이 설립한 비영리 기관인 MovieLabs 에서도 고품질 콘텐츠 보호를 목적으로 AES-128 또는 그 이상의 강도를 갖는 콘텐츠 암호화 알고리즘을 필수적으로 사용하도록 규정하였다. 본 논문에서는 디지털 방송 보안을 위해 널리 사용되고 있는 DVB-CSA 및 AES-128 보다 보안성능이 우수한 것으로 알려진 방송 콘텐츠 암호화 규격인 DVB-CSA ver3 표준 규격 기반으로 설계 및 구현된 스크램블 시스템에 대해 소개한다.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.591-594
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• 2005

This paper describes a design of AES-based CCM Protocol for IEEE 802.11i Wireless LAN Security. The CCMP core is designed with 128-bit data path and iterative structyre which uses 1 clock cycle per round operation. To maximize its performance, two AES cores are used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining) mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about 23% compared with conventional LUT-based design. The CCMP core designed in Verilog-HDL has 35,013 gates, and the estimated throughput is about 768Mbps at 66-MHz clock frequency.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.6
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• pp.717-726
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• 2002

In this study, we analyze hardware implementation schemes of the ARS(Advanced Encryption Standard-128) algorithm that has recently been selected as the standard cypher algorithm by NIST(National Institute of Standards and Technology) . The implementation schemes include the basic architecture, loop unrolling, inner-round pipelining, outer-round pipelining and resource sharing of the S-box. We used MaxPlus2 9.64 for VHDL design and simulations and FLEX10KE-family FPGAs produced by Altera Corp. for implementations. According to the results, the four-stage inner-round pipelining scheme shows the best performance vs. cost ratio, whereas the loop unrolling scheme shows the worst.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.5
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• pp.167-174
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• 2009

Recently, Li et al. proposed a new differential fault analysis(DFA) attack on the block cipher ARIA using about 45 ciphertexts. In this paper, we apply their DFA skill on AES and improve attack method and its analysis. The basic idea of our DFA method is that we recover intermediate ciphertexts in last round using final faulty ciphertexts and find out last round secret key. In addition, we present detail DFA procedure on AES and analysis of complexity. Furthermore computer simulation result shows that we can recover its 128-bit secret key by introducing a correct ciphertext and 2 faulty ciphertexts.

• KIISE Transactions on Computing Practices
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• v.22 no.7
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• pp.303-309
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• 2016

Recently, an increasing number of embedded processors such as ARM Mali begin to support GPGPU programming frameworks, such as OpenCL. Thus, GPGPU technologies that have been used in PC and server environments are beginning to be applied to the embedded systems. However, many embedded systems have different architectural characteristics compare to traditional PCs and low-power consumption and real-time performance are also important performance metrics in these systems. In this paper, we implement a parallel AES cryptographic algorithm for a modern embedded GPU using OpenCL, a standard parallel computing framework, and compare performance against various baselines. Experimental results show that the parallel GPU AES implementation can reduce the response time by about 1/150 and the energy consumption by approximately 1/290 compare to OpenMP implementation when 1000KB input data is applied. Furthermore, an additional 100 % performance improvement of the parallel AES algorithm was achieved by exploiting the characteristics of embedded GPUs such as removing copying data between GPU and host memory. Our results also demonstrate that higher performance improvement can be achieved with larger size of input data.