• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.6
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• pp.83-89
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• 2012

This paper proposes the design of a security-enhanced RFID authentication protocol which meets the privacy protection for tag bearers. The protocol which uses AES(Advanced Encryption Standard) cipher algorithm is based on a three-way challenge response authentication scheme. In addition, three different types of protocol packet formats are also presented by extending the ISO/IEC 18000-3 standard for realizing the security-enhanced authentication mechanism in RFID system environment. Through the comparison of security, it was shown that the proposed scheme has better performance in user data confidentiality, Man-in-the-middle replay attack, and replay attack, and forgery resistance, compared with conventional some protocols. In order to validate the proposed protocol, a digital Codec of RFID tag is also designed based on the protocol. This Codec has been described in Verilog HDL and also synthesized using Xilinx Virtex XCV400E device.

• The Journal of Korean Association of Computer Education
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• v.14 no.4
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• pp.53-61
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• 2011

Recently, the importance of information security is emphasized in IT related field. The agency related to information security implements the policies to emphasize the security and protection of the privacy. However, the issue in many companies and users is that awareness of security is still poor. Therefore, in this paper, we develope the learning program for AES(advanced encryption standard) block cipher, to raise the awareness of security. Also, wish to cause interest about AES cipher because user confirms process that is encryption/decryption through program of this paper directly and prove awareness about information security.

• Journal of IKEEE
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• v.22 no.1
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• pp.38-45
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• 2018

An integrated cryptographic processor that efficiently integrates ARIA, AES block ciphers and Whirlpool hash function into a single hardware architecture is described. Based on the algorithm characteristics of ARIA, AES, and Whirlpool, we optimized the design so that the hardware resources of the substitution layer and the diffusion layer were shared. The round block was designed to operate in a time-division manner for the round transformation and the round key expansion of the Whirlpool hash, resulting in a lightweight hardware implementation. The hardware operation of the integrated ARIA-AES-Whirlpool crypto-processor was verified by Virtex5 FPGA implementation, and it occupied 68,531 gate equivalents (GEs) with a 0.18um CMOS cell library. When operating at 80 MHz clock frequency, it was estimated that the throughputs of ARIA, AES block ciphers, and Whirlpool hash were 602~787 Mbps, 682~930 Mbps, and 512 Mbps, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1082-1088
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• 2005

Generating fast round key in AES Rijndael algorithm using three key sizes, such as 128, 192, and 256-bit keys is a critical factor to develop high throughput AES processors. In this paper, we propose on-the-fly round key generator which is applicable to the pipelined and non-pipelined AES processor in which cipher and decipher nodes must be implemented on a chip. The proposed round key generator has modular and area-and-time efficient structure implemented with simple connection of two key expander modules, such as key_exp_m and key_exp_s module. The round key generator for non-pipelined AES processor with support of three key lengths and cipher/decipher modes has about 7.8-ns delay time under 0.25um 2.5V CMOS standard cell library and consists of about 17,700 gates.

• Journal of Ubiquitous Convergence Technology
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• v.2 no.1
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• pp.12-17
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• 2008

In this paper, the 128bit AES block cipher algorithm OCB (Offset Code Book) mode for privacy and authenticity of high speed packet data was efficiently designed in C language level and was optimized to support the required capacity of contents server using high performance DSP. It is known that OCB mode is about two times faster than CBC-MAC mode. As an experimental result, the encryption / decryption speed of the implemented block cipher was 308Mbps, 311 Mbps respectively at 1GHz clock speed, which is 50% faster than a general design with 3.5% more memory usage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.578-580
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• 2017

IoT technology poses a lot of security threats. Various algorithms are thus employed in ensuring security of transactions between IoT devices. Advanced Encryption Standard (AES) has gained huge popularity among many other symmetric key algorithms due to its robustness till date. This paper presents a hardware based implementation of the AES algorithm. We present a four-stage pipelined architecture of the encryption and key generation. This method allowed a total plain text size of 512 bits to be encrypted in 46 cycles. The proposed hardware design achieved a maximum frequency of 1.18GHz yielding a throughput of 13Gbps and 800MHz yielding a throughput of 8.9Gbps on the 65nm and 180nm processes respectively.

• Journal of IKEEE
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• v.22 no.2
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• pp.233-241
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• 2018

This paper describes a lightweight implementation of a cryptographic processor supporting GCM (Galois/Counter Mode) authenticated encryption (AE) that is based on the two block cipher algorithms of ARIA and AES. It also provides five modes of operation (ECB, CBC, OFB, CFB, CTR) for confidentiality as well as the key lengths of 128-bit and 256-bit. The ARIA and AES are integrated into a single hardware structure, which is based on their algorithm characteristics, and a $128{\times}12-b$ partially parallel GF (Galois field) multiplier is adopted to efficiently perform concurrent processing of CTR encryption and GHASH operation to achieve overall performance optimization. The hardware operation of the ARIA/AES-GCM AE processor was verified by FPGA implementation, and it occupied 60,800 gate equivalents (GEs) with a 180 nm CMOS cell library. The estimated throughput with the maximum clock frequency of 95 MHz are 1,105 Mbps and 810 Mbps in AES mode, 935 Mbps and 715 Mbps in ARIA mode, and 138~184 Mbps in GCM AE mode according to the key length.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10B
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• pp.1491-1500
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• 2001

본 논문에서는 AES Rijndael 암호 알고리즘을 구현하는 암호 프로세서를 설계하였다. 하드웨어 공유를 통해 면적을 감소시키기 위해 1라운드 동작을 2개의 부분 라운드로 나누고 각 부분 라운드를 4 클록으로 구현하였다. 라운드 당 평균 5 클록의 연산 효율을 만들기 위해 인접한 라운드간에 부분 라운드 라이프라인 동작 기법을 적용하고, 키 설정 오버헤드 시간을 배제하기 위해, 암호 및 복호 동작의 라운드 키를 온라인 계산 기법을 사용하여 생성하였다. 그리고 다양한 응용 분야에 적용하기 위해, 128, 192, 256 비트의 3가지 암호 키를 모두 지원할 수 있도록 하였다. 설계된 암호 프로세서는 약 36,000개의 게이트로 구성되며 0.25$\mu\textrm{m}$ CMOS 공정에서 약 200Mhz의 동작 주파수를 가지며, 키 길이가 128 비트인 AES-128 ECB 동작 모드에서 약 512 Mbps의 암.복호 율의 성능을 얻을 수 있었다.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.3
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• pp.121-127
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• 2012

An integrated crypto engine for encryption and decryption of AES algorithm based on unified data-path architecture is efficiently designed and implemented in this paper. In order to unify the design of encryption and decryption, internal steps in single round is adjusted so as to operate with columns after row operation is completed and efficient method for a buffer is developed to simplify the Shift Rows operation. Also, only one S-box is used for both key expansion and crypto operation and Key-Box saving expended key is introduced provide the key required in encryption and decryption. The functional simulation based on ModelSim simulator shows that 164 clocks are required to process the data of 128bits in the proposed engine. In addition, the proposed engine is implemented with 6,801 gates by using Xilinx Synthesizer. This demonstrate that 40% gates savings is achieved in the proposed engine, compared to individual designs of encryption and decryption engine.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.5
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• pp.14-21
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• 2020

In order to provide confidential services between two communicating parties, block data encryption using a symmetric secret key is applied. A power analysis attack on a cryptosystem is a side channel-analysis method that can extract a secret key by measuring the power consumption traces of the crypto device. In this paper, we propose an attack model that can recover the secret key using a power analysis attack based on a deep learning convolutional neural network (CNN) algorithm. Considering that the CNN algorithm is suitable for image analysis, we particularly adopt the recurrence plot (RP) signal processing method, which transforms the one-dimensional power trace into two-dimensional data. As a result of executing the proposed CNN attack model on an XMEGA128 experimental board that implemented the AES-128 encryption algorithm, we recovered the secret key with 22.23% accuracy using raw power consumption traces, and obtained 97.93% accuracy using power traces on which we applied the RP processing method.