• 한국농공학회지
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• 제32권4호
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• pp.71-80
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• 1990

Model tests for the ultimate pullout resistance of anchorages and investigation of failure behaviors in cohesionless soil have been conducted. The factors affecting the anchorage are mostly the geometry of the system, and soil properties of sands. The main conclusions of the experimental work were as follows. 1. The load - displacement relationship can be a form of parabolic curve for all plates. 2. The change in ultimate pullout resistance of anchor is mostly affected by embedment ratio and size of anchor, and influenced to a lesser degree by its shape. 3. Critical embedment ratio which is defined as the failure mode changes from shallow to deep mode is increased with increasing height of anchor. 4. For a constant anchor height, as the width of anchor increases the ultimate pullout resistance also increases. However, considering the efficiency of anchor for unit area, width of anchor does not appear to have any sigrnificant contribution on increasing anchor city. 5. Anchor capacity has a linear relation to sand density for any given section and the rate of change increases as the section increases. Critical depth determining the failure patterns of anchor is decreased with a decrease of sand density. 6. With increasing inclination angle, size of anchor, and decreasing embedment ratio, the ultimate pullout resistance of anchor under inclined loading is significantly decreased. 7. The ultimate pullout resistance of double anchor, a method of improving single of anchor capacity, is influenced by the center - to - center spacing adjacent anchors. It is also found that tandem and parallel anchor rigging arrangements decrease the anchor system capacity to less than twice the single anchor capacity due to anchor interference.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제51권11호
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• pp.628-634
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• 2002

A capacitor-charging power supply using high frequency inverter technology is strongly recommended for the charging section of the pulsed power supplies. A high frequency inverter swiching makes the overall system size small. The command-charging feature can guarantee the higher reliability of switching function. The protection circuit can be easily included in the system and the good regulation of charging voltage can be acieved by the feedback system. Several modules can be stacked to supply required output power and a failed module can be easily replaced. A 50-kV, 35-kW capacitor charging power supply is developed. In this paper the detailed design and test results of a prototype unit are presented.

• 한국제4기학회지
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• 제17권1호
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• pp.27-37
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• 2003

한반도 동해 중부 해안에 위치한 강원도 고성군 문암리 신석기 유적지의 퇴적층의 퇴적환경은 퇴적물의 입도 특성과 광물 조성에 의하여 세 개의 퇴적층서 단위(Unit)로 구분되었다. 최하위 퇴적 층서 단위인 Uint 3은 하부의 사질층(S)과 상부의 니사질층(mS)으로 세분된다. 이 퇴적층은 해안 사구 모래가 퇴적된 후, 토양화 과정에 의해 소량의 니질(mud)을 함유하는 것으로 해석된다. Unit 3을 피복하는 Unit 2는 신석기 유물이 출토되며, 사층리 구조를 보이는 퇴적층으로 다시 하부의 니사질층(mS)과 상부의 사질층(S)으로 구분된다. 전체적으로 Unit 2 퇴적층은 해빈으로부터 바람에 의해 운반ㆍ퇴적된 전형적인 해안 사구(coastal dune) 퇴적층으로 해석된다. 최상위 퇴적층서 단위인 Unit 1은 역사질층(gS)으로 잔자갈이 함유되어 하부의 퇴적층보다 조립하며, 분급도 불량하다. 이 퇴적층은 해안사구 층으로 현재의 지표 유수와 식물의 영향을 받아 토양화 과정을 나타내는 것으로 해석된다. 이 문암리 유적지 사구층의 형성 연대는 기존의 해수면 변동 연구와 신석기 유물의 연대 분석 결과로 미루어 보아 현세 중기(middle Holocene, 약 7,800∼6,500 yr BP) 전후인 것으로 해석된다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.222-227
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• 2004

The sub-bitline (SBL) sensing voltage of a cell and total cell array can be measured by the method of SBL voltage evaluation method. The MOSAID tester can collect all SBL signals. The hierarchical bitline of unit cell array block is composed of the cell array of 2k rows and 128 columns, which is divided into 32 cell array sections. The unit cell array section is composed of the cell array of 64 rows and 128 columns. The average sensing voltage with 2Pr value of $5{\mu}C/cm^2$ and SBL capacitance of 40fF is about 700mV at 3.0V operation voltage. That is high compensation method for capacitor size degradation effect. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than $5{\mu}C/cm^2$.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제11권2호
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• pp.1043-1056
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• 2017

A styled document is a document that contains diverse decorating functions such as different font, colors, tables and images generally authored in a word processor (e.g., MS-WORD, Open Office). Compared to a plain-text document, a styled document enables a human to easily recognize a logical structure such as section, subsection and contents of a document. However, it is difficult for a computer to recognize the structure if a writer does not explicitly specify a type of an element by using the styling functions of a word processor. It is one of the obstacles to enhance document version management systems because they currently manage the document with a file as a unit, not the document elements as a management unit. This paper proposes a machine learning based approach to analyzing the logical structure of a styled document composing of sections, subsections and contents. We first suggest a feature vector for characterizing document elements from a styled document, composing of eight features such as font size, indentation and period, each of which is a frequently discovered item in a styled document. Then, we trained machine learning classifiers such as Random Forest and Support Vector Machine using the suggested feature vector. The trained classifiers are used to automatically identify logical structure of a styled document. Our experiment obtained 92.78% of precision and 94.02% of recall for analyzing the logical structure of 50 styled documents.

• 한국생산제조학회지
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• 제24권6호
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• pp.710-717
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• 2015

Projection stereolithography is an additive manufacturing method that uses beam projection to cure the photo-reactive resin used. The light source of a cross-section layer-form illuminates photo-curable resin for building a three-dimensional (3D) model. This method has high accuracy and a fast molding speed because the processing unit is a face instead of a dot. This study describes a Scalable Projection Stereolithography 3D Printing System for improving the accuracy of the stereolithography. In a conventional projection 3D printer, when printing a small sized model, many pixels are not used in the projection or curing. The proposed system solves this problem through an optical adjustment, and keeps using the original image as possible as filling the whole projection area. The experimental verification shows that the proposed system can maintain the highest level of precision regardless of the output size.

• 대한기계학회논문집
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• 제18권3호
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• pp.591-599
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• 1994

A design system for power transmission bevel gears(straight, zerol, and spiral) is developed, in which the strength and durability of bevel gears can be estimated and the size of bevel gears can be minimized by introducing optimal techniques. The size of bevel gear pair as the object function to be minimized is the volume of equivalent spur gear pair at mean normal section, and the design variables to be determined are considered as the number of teeth, face width, diametral pitch, and spiral angle in spiral bevel gear. The strength(bending strength, pitting resistance) according to the AGMA standards, geometrical quantities, and operating characteristics(interference of pinion, contact ratio, etc.) are considered as the constraints in design optimization. The optimization with these constraints becomes nonlinear problem and that is solved with ALM(Augmented Lagrange Multiplier) method. The developed design method is applied to the example designs of straight, zerol, and spiral bevel gears. The design results are acceptable from the viewpoint of strength and durability within the design ranges of all other constraint, and the bevel gears are designed toward minimizing the size of gear pair. This design method is easily applicable to the design of bevel gears used as power transmitting devices in machineries, and is expected to be used for weight minimization of bevel gear unit.

• 전력전자학회논문지
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• 제19권5호
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• pp.399-406
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• 2014

This study investigates the structure and operation of the ITER VS converter and proposes a sequence control method for six series-connected VS converters to reduce reactive power. The operation and the proposed sequence control method are verified through RTDS simulation. The ITER VS converter must supply voltage/current to the superconducting magnets for plasma current vertical stabilization, and the four-quadrant operation must proceed without a zero-current discontinuous section. The operation mode of the VS converter is separated into a 12- and 6-pulse circulating current and transition modes according to the size of the load current. The output voltage of the unit VS converter is limited because of the rated voltage; however, the superconducting coil must increase the operating output voltage. Thus, the VS converter must be connected in a 6-series to provide the required operating output voltage. The output voltage of the VS converters is controlled continuously; however, reactive power is limited within a minimized value of the grid. In this study, the unit converter is compared with converters connected in a 6-series to determine a suitable sequence control method. The output voltage is the same in all cases, but the maximum reactive power is reduced from 100% to 73%. This sequence control method is verified through RTDS simulation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.84-87
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• 2000

In this paper, a high gain-broad bandwidth MMIC distributed amplifier was designed using cascaded single section distributed amplifier configuration. The PHEMT for this studies was fabricated at our lab The PHEMT has a 0.2 $\mu\textrm{m}$ gate length. a 80 $\mu\textrm{m}$ unit gate width and 4 gate fingers. A designed MMIC amplifier have higher S$\sub$21/ gain than the common distributed amplifier using the same number of active devices. From the simulated result, we obtained that the S$\sub$21/ gain of DC ∼ 20 GHz bandwidth was 15.6 dB and flatness was ${\pm}$0.9 dB, and input and output reflection coefficient were lower than -8 dB. The simulated gain shows an improvement 7.3 dB compared with those of conventional distributed amplifier. And the chip size is 2.0 ${\times}$ 1.2 $\textrm{mm}^2$.

• 한국전자통신학회논문지
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• 제5권1호
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• pp.58-65
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• 2010

본 연구는 선불 또는 후불 교통카드 사용에 있어서 사용불가 카드 또는 사용 가능 카드 정보만을 구성하여 시스템 운영의 응답 시간을 단축하여 선별하는 방법과 그 시스템에 관한 것으로 기존의 카드 방식에서 제안하고 있는 방법의 차이점을 개선하므로 정보를 구성하고 있는 용량을 개선하여 처리 용량 대비 업데이트 속도를 개선하여 시스템의 효율성을 향상 시키고자 하였다. 이에 본 연구에서는 각각의 파일은 다수의 섹션으로 구성하고 또한 각 섹션은 다수개의 블록으로 구성하고 각 블록은 다수개의 셀 단위의 크기로 분할하여 구성한 인덱스 부와 사용 불가 또는 사용 가능 카드 정보 중에 더 낮은 비율을 차지하는 정보로 구성하는 데이터 부의 영역으로 구성하여 시스템의 성능을 개선하였다.