• Journal of Power Electronics
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• v.16 no.1
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• pp.182-189
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• 2016

Fault detection is the research focus and priority in this study to ensure the high reliability of a proposed three-level inverter. Kernel principal component analysis (KPCA) has been widely used for feature extraction because of its simplicity. However, highlighting useful information that may be hidden under retained KPCs remains a problem. A weighted KPCA is proposed to overcome this shortcoming. Variable contribution plots are constructed to evaluate the importance of each KPC on the basis of sensitivity analysis theory. Then, different weighting values of KPCs are set to highlight the useful information. The weighted statistics are evaluated comprehensively by using the improved feature eigenvectors. The effectiveness of the proposed method is validated. The diagnosis results of the inverter indicate that the proposed method is superior to conventional KPCA.

• Journal of Sensor Science and Technology
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• v.19 no.1
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• pp.1-7
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• 2010

Electrostatic capacitance measurement method in a fine hose was proposed, in which two ring-type electrodes were disposed on the hose in the direction of fluid flow instead of the conventional face-to-face electrodes. With the proposed electrode structure, we realized a Ringer's solution exhaustion detector for an IV(invasive vein) injection set. On a 4 mm-diameter hose of IV set, we disposed two ring-type electrodes of 10 mm width at a distance of 5 mm each other and obtained 0.72 pF and 2.51 pF for air and 10 % dextrose Ringer's solution in the hose, respectively. The capacitance between the two electrodes varied with the hose-wraparound coverage of electrode as well as the width of electrode and the distance between the electrodes. For hose-wraparound electrode coverage of 75 %, the capacitance varied from 0.62 pF to 1.98 pF with the Ringer's solution level between the two electrodes. A charge amplifier converted the capacitance. variation into electric signal and a comparator was used to detect whether Ringer's solution was exhausted or not. The result was delivered to a host using a RF transmitter with 320 MHz carrier frequency.

• International Journal of CAD/CAM
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• v.7 no.1
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• pp.11-20
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• 2007

A topology optimization methodology, named "smooth boundary topology optimization," is proposed to overcome the shortcomings of cell-based methods. Material boundary is represented by B-spline curves and their control points are considered as design variables. The design is improved by either creating a hole or moving control points. To determine which is more beneficial, a selection criterion is defined. Once determined to create a hole, it is represented by a new B-spline and recognized as a new boundary. Because the proposed method deals with the control points of B-spline as design variables, their total number is much smaller than cell-based methods and it ensures smooth boundaries. Differences between our method and level set method are also discussed. It is shown that our method is a natural way of obtaining smooth boundary topology design effectively combining computer graphics technique and design sensitivity analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.185-197
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• 2001

Recently, the design method by VHDL coding and synthesis has been used widely. As the integration ratio increases, the amount design by VHDL at a time also increases so many coding errors occur in a design. Thus, lots of time and effort is dissipated to detect those coding errors. This paper proposed a method to verify the coding errors in VHDL behavioral-level designs. As the methodology, we chose the method to detect the coding error by applying the generated set of verifying patterns and comparing the responses from the error-free case(gold unit) and the real design. Thus, we proposed an algorithm to generate the verifying pattern set for the coding errors. Verifying pattern generation is peformed for each code and the coding errors are classified as two kind: condition errors and assignment errors. To generate the patterns, VHDL design is first converted into the corresponding CDFG(Control & Data Flow Graph) and the necessary information is extracted by searching the paths in CDFG. Path searching method consists of forward searching and backward searching from the site where it is assumed that coding error occurred. The proposed algorithm was implemented with C-language. We have applied the proposed algorithm to several example VHDL behavioral-level designs. From the results, all the patterns for all the considered coding errors in each design could be generated and all the coding errors were detectable. For the time to generate the verifying patterns, all the considered designed took less than 1 ［sec］ of CPU time in Pentium-II 400MHz environments. Consequently, the verification method proposed in this paper is expected to reduce the time and effort to verify the VHDL behavioral-level designs very much.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.20 no.44
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• pp.257-261
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• 1997

Patents often serve as leading indicators of technological change. This patenting activity reflected R&D (Research & Development) of new technology. The purpose of this study is to set up a forecasting model that anticipate the number of domestic patent applications and the number of patents granted relating to R&D inputs (R&D expenditure, R&D manpower) at the level of three industrial sectors in Korea : electrical-electronic, machinery, chemical etc. In this study, forecasting models were used trend extrapolation and a set of regressions. Both Theil's inequality coefficient and MAE(Mean Absolute Error) were utilized to test the precision of predicted value. The patent data and the R&D data were based on Indicators of Industrial Technology data throught 1980 to 1996. The major results obtained in this study are as follows (1) The regression model is more useful for forecasting the trends of the number of patent applications and patents granted than the trend extrapolation method. (2) The variance of Theil's inequality is smaller in patent applications than in patent granted.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.28-31
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• 2009

In this paper, a new approach for solid texture synthesis from input volume data is presented. In the pre-process, feature vectors and a similarity set were constructed for input volume data. The feature vectors were used to construct neighboring vectors for more accurate neighborhood matching. The similarity set which recorded 3 candidates for each voxel helped more effective neighborhood matching. In the synthesis process, the pyramid synthesis method was used to synthesize solid textures from coarse to fine level. The results of the proposed approach were satisfactory.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.387-390
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• 2000

This paper proposes an efficient and accurate power estimation method for Application Specific Instruction set Processors (ASIPs). Proposed method takes advantage of the data types of variables in application program to be executed on the ASIP. According to the experimental results, the efficiency of proposed method was more than 1000 times as high as that of conventional RTL based power estimation method, and the estimation error was within 10% compared to a conventional gate-level accurate power estimation method

• Journal of the Korean Society for Precision Engineering
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• v.27 no.1
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• pp.58-63
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• 2010

A new contact force estimation technique is proposed. Keeping the contact force at a certain level between finishing tool and the object is essential since the quality of the finished surface is very sensitive to the contact force during the finishing process. However, the contact force measurement cannot be obtained by simply installing load cells under machine table or in the middle of tool linkage. The reason is that the weight of the machine table and the tool linkage are much heavier than the force to be measured. To that end, a method for estimating disturbance is proposed for a system that is similar to the mechanism of the finishing machine, and the same method is applied to estimate the contact force of the brush-type finishing machine. To verify the effectiveness of the proposed method, a small scale test set-up has been built and the method has been tested.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.815-818
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• 1998

Hardware formal verification involves the use of analytical techniques to prove that the implementation of a system confroms to the specification. The specification could be a set of properties that the system must have or it could be an alternative representation of the system behavior. We can represent our behavioral specification to be written in VHDL coding. In this paper, we proposed a new hardware design verification method. For theis method, we assumed that a verification pattern already exists and try to make an algorithm to find a place where a design error occurred. This method uses an hierarchical approach by making control flow graph(CFG) hierarchically. From the simulation, this method was turned out to be very effective that all the assumed design errors could be detected.

• Journal of Korea Multimedia Society
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• v.17 no.11
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• pp.1279-1285
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• 2014

In this paper, we propose on image encryption method which uses NC(Non-linear Cycle) and 2D CAT(Two-Dimensional Cellular Automata Transform) in sequence to encrypt medical images. In terms of the methodology, we use NC to generate a pseudo noise sequence equal to the size of the original image. We then conduct an XOR operation of the generated sequence with the original image to conduct level 1 NC encryption. Then we set the proper Gateway Values to generate the 2D CAT basis functions. We multiply the generated basis functions by the altered NC encryption image to conduct the 2nd level 2D CAT encryption. Finally, we verify that the proposed method is efficient and extremely safe by conducting an analysis of the key spatial and sensitivity analysis of pixels.