• 제목/요약/키워드: A and B paper size

검색결과 1,431건 처리시간 0.032초

영상의 국부적 성질을 이용한 가변 크기 블록 정합 알고리즘 (A Variable Size Block Matching Algorithm Using Local Characteristics of Images)

  • 김진태;최종수;박래홍
    • 전자공학회논문지B
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    • 제29B권7호
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    • pp.62-69
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    • 1992
  • The conventional BMA is performed with the fixed block size. For better performance at low bitrate, the block size is required to be large in relatively stationary area, while small in moving area. Thus, in this paper, a video coding technique using variable block size model is proposed. It decides the block size based on the degree of local motion defined by the local mean and variance of blocks. Computer simulation shows that the proposed method gives comparable performance to the conventional one with less bits required for motion vector coding.

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크기가 다양한 bin-packing 문제에 대한 algorithm

  • 강장하;박성수
    • 한국경영과학회:학술대회논문집
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    • 대한산업공학회/한국경영과학회 2000년도 춘계공동학술대회 논문집
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    • pp.205-206
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    • 2000
  • In this paper, we consider variable sized bin packing problem, where the objective is not to minimize the total space used in the packing but to minimize the total cost of the packing when the cost of unit size of each bin does not increase as the bin size increases. A heuristic algorithm is described, and analyzed in two special cases: 1) b$\sub$m/|…|b$_1$and w$\sub$n/|…|w$_1$, and 2) b$\sub$m/|…|b$_1$, where b$\sub$i/ denotes the size of i-th type of bin and w$\sub$j/ denotes the size of j-th item. In the case 1), the algorithm guarantees optimality, and in the case 2), it guarantees asymptotic worst-case performance bounds of l1/9.

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CAD 형상 데이터를 이용한 비정렬 격자 자동 생성을 위한 격자셀 크기 지정 기법 (A NEW CELL SIZING METHOD FOR AUTOMATIC UNSTRUCTURED GRID GENERATION USING CAD SURFACE DATA)

  • 이봉주;김병수
    • 한국전산유체공학회:학술대회논문집
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    • 한국전산유체공학회 2007년도 추계 학술대회논문집
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    • pp.120-125
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    • 2007
  • In this paper a new cell sizing method is proposed. The new method calculates cell size at a point using given size control elements directly without the aid of background grid as other cell sizing algorithms do. The calculation method and related definitions are described in detail, and typical cell sizing results are given.

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신문에 끼워진 상업용 전단지의 특성 (제 1보) - 발행업종별 전단지의 크기 및 인쇄 형태 - (Characteristics of Commercial Leaflets Sandwiched in Newspaper (Part 1) - The Size and Printing Types of Leaflets according to Business -)

  • 윤승락
    • 펄프종이기술
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    • 제45권6호
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    • pp.55-63
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    • 2013
  • To offer a basic information for the fibers of commercial leaflets, authors examined and analyzed the distribution, size, and printing types of leaflets sandwiched in the newspaper. The number of different leaflet size were almost 30 in two years including B5 ($182{\times}257mm$), A4 ($210{\times}297mm$), B4, ($257{\times}364mm$), A3 ($297{\times}420mm$), and large flyers such as $545{\times}395mm$, and $790{\times}550mm$. The number of different leaflets size were 25 in 2011, which was reduced to 15 in 2012. Both the number and amount of the leaflets were reduced. The high quality leaflets were issued and distributed in the corporate sector and the leaflets issued in other sectors such as shopkeeping, restaurant business, educational institutions were one-sided leaflets printed on single side of the paper. Compared to the previous year, large stores showed the increased number of leaflets but the number of leaflets from restaurant business and educational institutions and building trade were decreased.

플래시 메모리 상에서 B+-트리 노드 크기 증가에 따른 성능 평가 (Effect of Node Size on the Performance of the B+-tree on Flash Memory)

  • 박동주;최해기
    • 정보처리학회논문지A
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    • 제15A권6호
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    • pp.325-334
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    • 2008
  • 플래시 메모리는 크기가 작고 적은 전력을 사용하며 충격에 강하기 때문에 휴대폰, MP3 플레이어, PDA와 같은 이동 기기에 널리 사용되고 있다. 또한, 노트북과 개인용 컴퓨터에서 사용하던 하드디스크를 플래시 메모리로 교체하려는 시도도 진행되고 있다. 최근에는 플래시 메모리 저장 시스템에서 대용량의 데이터를 효율적으로 검색하기 위한 플래시 메모리용 $B^+$-트리 인덱스를 개발하려는 연구가 이루어지고 있다. 이러한 연구는 $B^+$-트리에 키의 삽입 또는 삭제 시 발생하는 "덮어쓰기"를 최소화하는데 초점을 두고 있다. 그러나 이것뿐만 아니라 하나의 $B^+$-트리 노드에 할당되는 물리적 페이지의 크기도 $B^+$-트리 성능에 영향을 줄 수 있다. 본 논문에서는 다양한 실험을 통해 노드 크기에 따른 $B^+$-트리의 구축 성능, 검색 성능, 그리고 저장 공간 사용량을 비교 및 분석한다. 노드에 키 삽입 시 정렬 및 비정렬 알고리즘을 제시하며, 또한 효율적인 노드 검색을 위한 적절한 인덱스 노드 헤드 구조를 제안한다.

좌우 트렌치를 구비한 분리 주기 테이퍼 도파로 모드 크기 변환기의 설계 및 성능 분석 (Design and analysis of a mode size converter composed of periodically segmented taper waveguide surrounded by trenches)

  • 박보근;정영철
    • 대한전자공학회논문지SD
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    • 제41권12호
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    • pp.43-49
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    • 2004
  • 본 논문에서는 슈퍼하이델타(Super High Delta) 실리카 광도파로와 단일 모드 광섬유 사이의 결합손실을 줄이기 위한 모드 크기 변환기를 설계하였다. 새로운 모드 크기 변환기는 물리적 크기를 최소화하기 위해 주기적으로 분리된 테이퍼 도파로를 사용하였으며 공정을 간단히 하기 위해 수평형 테이퍼를 사용하였다. 또한 결합손실을 개선하기 위해 모드 크기 변환기 주변에 트렌치 구조를 삽입하였다. 최적의 모드 크기 변환기 설계에서 결합손실은 트렌치 구조가 삽입되지 않은 경우는 0.33dB/point 이며 트렌치가 삽입된 경우는 0.2dB/point이다.

이동 로보트의 계단 승월을 위한 계단 크기 인식 기법에 관한 연구 (A Study on the Recognition Method of the Stair Size for the Climbing Mobile Robot)

  • 김승범;이응혁;김병수;김승호;민홍기;홍승홍
    • 전자공학회논문지B
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    • 제32B권10호
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    • pp.1269-1279
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    • 1995
  • A mobile robot in a nuclear power plant is usually needed to equip the ability of going up and down stairs for a some kind of inspection. For this purpose, it is necessary for the mobile robot to figure out the size of stairs laid on a navigation path to gurantee robot's moving freely. In this paper, to measure the size of stairs existing in front of a mobile robot we designed the stair size recognition unit which can measure the stair's height and width using an ultrasonic sensor and/or a CCD camera. Also to obtain higher reliability of ultrasonic sensing data we proposed the horizontal sensing method. On the assupmtions that the mobile robot generates a trajectory while ascending stairs, we simulated it on a IBM compatible computer. The result showed that the suggested method satisfied our purpose. In a stair size estimation, the detected stair's height error was about .+-.3mm, and width was about .+-.5mm.

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A Simple Dual Band Filter Design with 0603 Case Size using IPD Technology for 1.8 GHz and 2.5 GHz DC-block Application

  • Li, De-Zhong;Wang, Cong;Kyung, Gear Inpyo;Kim, Nam-Young
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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    • pp.385-386
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    • 2008
  • In this paper, a simple dual band filter chip is designed with 0603 case size using IPD technology. The dual-band filter achieves high frequency band at 2.5 GHz and low frequency band at 1.8 GHz. The insertion losses in high frequency band and low frequency band are -0.195 dB and -0.146 dB, respectively. The return losses in these bands are -22.7 dB and -22.8 dB, respectively. The simple dual-band filter based on SI-GaAs substrate is designed within die size of about 1.3 $mm^2$.

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도공층의 공극과 인쇄적성에 관한 연구(제3보) -라텍스의 특성이 미치는 영향- (Studies on the Pore of Coating Layer and Printability(III) -Effects of Properties of Latices on Pore of Coating Layer-)

  • 이용규;김창근
    • 펄프종이기술
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    • 제33권2호
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    • pp.41-48
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    • 2001
  • This paper was made to evaluate the effect of the type of latex for coating on the printability by investigating the structure of pore such as the pore fraction, the number of pores, pore size and distribution of coated paper. The coated structure is mainly depend on the results of interaction between pigment and binder. It means that the structure of pore formed is chiefly affected by the type of latex. This physical properties of pore have a close relation with ink set-off associated with the drying rate, the speed of penetration of ink into base paper and printing gloss. Therefore it was necessary to find out the relationship between pore structure and the performance of printability by modifying the type of latex to vary the pore structure of coated paper. Acrylic latex was superior to S/B latex in the sedimentation volume, compressibility, smoothness, pore fraction and its number, the weight of transferred ink onto the coated paper and ink repellance. In contrast, water retention and ink setting were not good. in the comparison of anionic and amphoteric latex, amphoteric latex showed better performance in the thickness, smoothness, pore fraction and its number, pore size, the weight of ink transmitted and K&N ink receptivity, etc.

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A High-Linearity Low-Noise Reconfiguration-Based Programmable Gain Amplifier

  • Han, Seok-Kyun;Nguyen, Huy-Hieu;Lee, Sang-Gug
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제13권4호
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    • pp.318-330
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    • 2013
  • This paper presents a high-linearity low-noise small-size programmable gain amplifier (PGA) based on a new low-noise low-distortion differential amplifier and a proposed reconfiguration technique. The proposed differential amplifier combines an inverter-based differential pair with an adaptive biasing circuit to reduce noise and distortion. The reconfiguration technique saves the chip size by half by utilizing the same differential pair for the input transconductance and load-stage, interchangeably. Fabricated in $0.18-{\mu}m$ CMOS, the proposed PGA shows a dB-linear control range of 21dB in 16 steps from -11 dB to 10 dB with a gain error of less than ${\pm}0.33$ dB, an IIP3 of 7.4~14.5 dBm, a P1dB of -7~1.2 dBm, a noise figure of 13dB, and a 3-dB bandwidth of 270MHz at the maximum gain, respectively. The PGA occupies a chip area of $0.04mm^2$ and consumes only 1.3 mA from the 1.8 V supply.