• Journal of Korea Multimedia Society
• /
• v.21 no.11
• /
• pp.1271-1278
• /
• 2018

The NDT using ultrasonic is largely divided into A-Scan and C-Scan methods. Since A-Scan method is subject to subjective judgement by trained personnel, C-Scan method has been introduced, which presents the weld area in two dimensions by placing the transducers two dimensionally used in the A-Scan method. Therefore, it is necessary to develop equipment that can provide weld quality without the help of a welding expert and the presentation of effective C-Scan images. Thus, in this paper, the algorithms that express a low resolution 2-dimensional gray image formed by C-Scan method as a high-resolution color C-Scan image and automatically determine the weld quality from the generated C-Scan color image. The high resolution color C-Scan images proposed in this paper allow the exact shape of the weld point to be expressed, and an objective algorithm to use this image to automatically determine weld quality.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.892-895
• /
• 2011

Power consumption during testing System-On-Chip (SOC) are becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• ETRI Journal
• /
• v.38 no.3
• /
• pp.479-486
• /
• 2016

System-on-chip (SoC) designs have a number of flip-flops; the more flip-flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical-aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout-aware flip-flop insertion and scan shift operation-aware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state-of-the-art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.

• Journal of Korea Multimedia Society
• /
• v.20 no.10
• /
• pp.1662-1670
• /
• 2017

A-Scan NDT equipment is widely used in the industrial field because it is inexpensive and easy to carry but it is necessary to have a skilled inspection specialist who is trained to analyze the waveform of ultrasonic signal. Since the welding quality is judged subjectively by the specialist, there is a problem in the reliability of the quality. In the C-Scan NDT which overcomes the shortcomings of the A-Scan, welding part can be represented in the form of two dimensional image by combining one dimensional ultrasonic waveform so that the quality of welding can be grasped without the help of specialist. In order to develop C-Scan NDT, it is necessary to develop an array type two dimensional transducer and an algorithm to composing image by combining ultrasonic signals generated from a two dimensional transducer. In addition, the noise component must be minimized in the ultrasonic signal in order to display the quality of welding in the form of images. Therefore we propose a method to remove noise component from the ultrasonic wave and construct a two dimensional ultrasonic image.

• Proceedings of the Korean Society of Propulsion Engineers Conference
• /
• 2006.05a
• /
• pp.264-267
• /
• 2006

One of the serious problems that make the flaw identification in a multi-layered thick composite panel more difficult is the interferenceeffect of the upper layer. To take care of such a problem, here we propose an image enhancement approach that can get rid of such an interference effect to ultrasonic C-scan images by a normalization of the acquired signals by a reference signals, and demonstrate its performance in the experiments. Specifically, three specimens with artificial flaws are prepared and ultrasonic C-scan images are acquired experimentally to eliminate the undesired interference effect. Cleat successes are observed in the present study demonstrating the high potential of the proposed algorithm as a practical image enhancement tool in many practical situations.

• BMB Reports
• /
• v.39 no.2
• /
• pp.167-170
• /
• 2006

Bovine adenosine deaminase undergoes a nondenaturational conformational change at $29^{\circ}C$ upon heating which is characterized by a large increase in heat capacity. We have determined the transition state thermodynamics of the conformational change using a novel application of differential scanning calorimetry (DSC) which employs very slow scan rates. DSC scans at the conventional, and arbitrary, scan rate of $1^{\circ}C/min$ show no evidence of the transition. Scan rates from 0.030 to $0.20^{\circ}C/min$ reveal the transition indicating it is under kinetic control. The transition temperature $T_t$ and the transition temperature interval ${\Delta}T$ increase with scan rate. A first order rate constant $k_1$ is calculated at each $T_t$ from $k_1\;=\;r_{scan}/{\Delta}T$, where $r_{scan}$ is the scan rate, and an Arrhenius plot is constructed. Standard transition state analysis reveals an activation free energy ${\Delta}G^{\neq}$ of 88.1 kJ/mole and suggests that the conformational change has an unfolding quality that appears to be on the direct path to the physiological-temperature conformer.

• Investigative Magnetic Resonance Imaging
• /
• v.19 no.4
• /
• pp.212-217
• /
• 2015

Purpose: For a single time-point hyperpolarized $^{13}C$ magnetic resonance spectroscopy imaging (MRSI) of animal models, scan-time window after injecting substrates is critical in terms of signal-to-noise ratio (SNR) of downstream metabolites. Pre-scans of time-resolved magnetic resonance spectroscopy (MRS) can be performed to determine the scan-time window. In this study, based on two-site exchange model, protocol-specific simulation approaches were developed for $^{13}C$ MRSI and the optimal scan-time window was determined to maximize the SNR of downstream metabolites. Materials and Methods: The arterial input function and conversion rate constant from injected substrates (pyruvate) to downstream metabolite (lactate) were precalibrated, based on pre-scans of time-resolved MRS. MRSI was simulated using two-site exchange model with considerations of scan parameters of MRSI. Optimal scan-time window for mapping lactate was chosen from simulated lactate intensity maps. The performance was validated by multiple in vivo experiments of BALB/C nude mice with MDA-MB-231 breast tumor cells. As a comparison, MRSI were performed with other scan-time windows simply chosen from the lactate signal intensities of pre-scan time-resolved MRS. Results: The optimal scan timing for our animal models was determined by simulation, and was found to be 15 s after injection of the pyruvate. Compared to the simple approach, we observed that the lactate peak signal to noise ratio (PSNR) was increased by 230%. Conclusion: Optimal scan timing to measure downstream metabolites using hyperpolarized $^{13}C$ MRSI can be determined by the proposed protocol-specific simulation approaches.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.3
• /
• pp.345-355
• /
• 2014

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

• Journal of the Korean Magnetics Society
• /
• v.26 no.3
• /
• pp.92-98
• /
• 2016

To aim of this study was to assess the full scan and half scan of imaging with half scan factor. Patients without a cerebral vascular disease (n = 30) and were subject to the full scan half scan, and set a region of interest in the cerebral artery from the three regions (C1, C2, C3) in the range of 7 to 8 mm. MIP (maximum intensity projection) to reconstruct the images in signal strength SNR (signal to noise ration), PSNR (peak signal noise to ratio), RMSE (root mean square error), MAE (mean absolute error) and calculated by paired t-test for use by statistics were analyzed. Scan time was half scan (4 minutes 53 seconds), the full scan (6 minutes 04 seconds). The mean measurement range (7.21 mm) of all the ROI in the brain blood vessel, was the SNR of the first C1 is completely scanned (58.66 dB), half-scan (62.10 dB), a positive correlation ($r^2=0.503$), for the second C2 SNR is completely scanned (70.30 dB), half-scan (74.67 dB) the amount of correlation ($r^2=0.575$), third C3 of a complete scan SNR (70.33 dB), half scan SNR (74.64 dB) in the amount of correlation between the It was analyzed with ($r^2=0.523$). Comparative full scan with half of SNR ($4.75{\pm}0.26dB$), PSNR ($21.87{\pm}0.28dB$), RMSE ($48.88{\pm}1.61$), was calculated as MAE ($25.56{\pm}2.2$). SNR is also applied to examine the half-scans are not many differences in the quality of the two scan methods were not statistically significant in the scan (p-value > .05) image takes less time than a full scan was used.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.3
• /
• pp.286-292
• /
• 2012

Scan techniques are almost mandatorily adopted in designing current System-on-a-Chip (SoC) to enhance testability, but inadvertently secret keys can be stolen through the scan test channels of crypto SoCs. An efficient scan design technique is proposed in this paper to protect the secret key of an Advanced Encryption Standard (AES) core embedded in an SoC. A new instruction is added to IEEE 1149.1 boundary scan to use a fake key instead of user key, in which the fake key is chosen with meticulous care to improve the testability as well. Our approach can be implemented as user defined logic with conventional boundary scan design, hence no modification is necessary to any crypto IP core. Conformance to the IEEE 1149.1 standards is completely preserved while yielding better performance of area, power, and fault coverage with highly robust protection of the secret user key.