• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.1101-1107
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• 2004

This paper presents an optimization algorithm and technique for designing parallel Cyclic Redundancy Check (CRC) circuit, which is most widely adopted for error detection A new heuristic algorithm is developed to find as many shared terms as possible, thus eventually to minimize the number and level of the exclusive-or logic blocks in parallel CRC circuits. 16-bit and 32-bit CRC generators are designed with different types of Programmable Logic Devices, and it has been found that our new algorithm and architecture significantly reduce the delay.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.124-131
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• 2014

This paper describes a design of an adaptive baseband modem based on TDMA(time division multiple access) with a relay protocol function for wireless personal area networks. The designed baseband modem is controlled by a master synchronization signal and can be configured a relay network up to 14 hops. For efficient data relay communications, the internal buffer design is optimized by implementing a priority memory bus controller to a single port memory. And the priority memory bus controller is also designed to minimize the number of synthesized logic gates. To implement the synchronization function of the narrowband TDMA relay communication, the number of gates has been reduced by dividing the frame synchronization circuits and the network slot synchronization circuits. By using these methods, the number of gates are used about 37%(34,000 gates) on Xilinx FPGA XC6SLX9 which has 90,000 gates. For the 1024-bit frame size with a 32-bit synchronization word, the communication reception rate is 96.4%. The measured maximum transmission delay of the designed baseband modem is 230.4 msec for the 14-hop relay communication.

• Journal of Satellite, Information and Communications
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• v.9 no.2
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• pp.18-22
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• 2014

Satellite communications consist of communications between base stations of the ground and satellites. For efficient satellite communications, ground networks should be organically utilized. Grid networks are frequently used in and outside the country for wireless communications. The performance of wireless communications is determined by mobility, topography, and jamming signals. Therefore, continuous studies of grid networks are necessary for the utilization of next period satellite networks. Since military communications are used based on wireless systems, they can be considered as a sample of utilization of grid networks. Therefore, this paper presented the results of simulations conducted for the improvement of the performance of the grid networks used in military communications that employing the OSPF, a popular routing protocol for military applications. First we investigate the effects of changing the bit error rate (BER) and number of routers. Then we discuss the effects of maximum segment size (MSS) on network behavior and stability. In this way, we can determine the appropriate MSS for a grid network under various values of BER and number of routers. Such results can be also applied to commercial grid network evaluations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12C
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• pp.965-970
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• 2010

In the NAND flash memory storing two bits per cell, data is discriminated among four levels of electrical charges. We refer to these four levels as E, P1, P2, and P3 from the low voltage. In the statistics, many errors occur when E and P3 are stored at the next cells. Therefore, we propose a coding scheme for avoiding E-P3 or P3-E data patterns. We investigate two modulation codes for 9/10 code (9 bit input and 5 symbol codeword) and 11/12 code (11 bit input and 6 symbol codeword).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1123-1131
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• 2005

In this paper, optimal position of optical phase conjugator (OPC) for best compensating distorted WDM channels due to both chromatic dispersion and self phase modulation (SPM) in $8{\times}40$ Gbps WDM systems is numerically investigated, and the eye opening penalty (EOP) and bit error rate (BER) characteristics of overall WDM channels at this position is investigated, comparing with that in case of OPC placed at mid-way of total transmission length. It is confirmed that the compensation extents in WDM system with OPC is more improved by the shifting OPC position from the mid-way of total transmission length, depending on the modulation format and fiber dispersion coefficient. Ant it is confirmed that, from a viewpoint of the reception performance, EOP of each channel is more or less different with one another, but the BER characteristics of overall channels are almost equal.

• Journal of Satellite, Information and Communications
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• v.9 no.2
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• pp.23-27
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• 2014

In this paper, we propose a soft demapping method for 64-ary APSK in the DVB-S3 system. The proposed method in this paper uses the hard decision threshold (HDT) line for each constituent bit in a symbol, and calculates the soft bit information with the distance between the HDT line and the detected symbol. If the HDT lines are defined in a simple manner, the complexity to estimate soft information can be largely reduced compared with the maximum likelihood detection (MLD) which has an exponential complexity. By considering this, we first derive HDT lines for each constituent bit for a 64-APSK symbol, and propose a method to calculate soft bit information. We simulate the BER performance of the proposed scheme by using a turbo codes which requires soft-input-soft-output information, and compare it that of the MLD. The result show that the proposed scheme produces approximating performance to MLD with largely reduced complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.11C
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• pp.1037-1043
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• 2006

In this paper, we introduce a two-dimensional modulation code for holographic data storage systems(HDSS), which is a candidate for the next generation data storage system. The two-dimensional(2D) intersymbol interference(ISI) induces higher bit error rate(BER). The balanced number of zeros(dark) and ones(light) in each page reduces inter-page interference(IPI). The code rate is 519. Although the proposed code has higher code rate than other 2D code with rate 4/9, the BER performances of two codes are similar.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.2
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• pp.86-91
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• 2014

Holographic data storage (HDS) has a number of advantages, including a high transmission rate through the use of a charge coupled device array for reading two-dimensional (2D) pixel image data, and a high density capacity. HDS also has disadvantages, including 2d intersymbol interference by neighboring pixels and interpage interference by multiple pages stored in the same holographic volume. These problems can be eliminated by modulation codes. We propose a 7/9 error-correcting modulation code that exploits a Viterbi-trellis algorithm and has a code rate larger (about 0.778) than that of the conventional 6/8 balanced modulation code. We show improved performance of the bit error rate with the proposed scheme compared to that of the simple 7/9 code without the trellis scheme and the 6/8 balanced modulation code.