• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.4
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• pp.409-416
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• 2014

In H/W implementation for the finite field, the use of normal basis has several advantages, especially the optimal normal basis is the most efficient to H/W implementation in $GF(2^m)$. The finite field $GF(2^m)$ with type I optimal normal basis(ONB) has the disadvantage not applicable to some cryptography since m is even. The finite field $GF(2^m)$ with type II ONB, however, such as $GF(2^{233})$ are applicable to ECDSA recommended by NIST. In this paper, we propose a bit-parallel multiplier over $GF(2^m)$ having a type II ONB, which performs multiplication over $GF(2^m)$ in the extension field $GF(2^{2m})$. The time and area complexity of the proposed multiplier is the same as or partially better than the best known type II ONB bit-parallel multiplier.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1993-1999
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• 2011

This paper describes a design of area-efficient/low-power cryptographic processor for HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a 0.35-${\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.1
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• pp.1-6
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• 2021

In this paper, in order to mitigate ISI(inter-symbol interference) in a diffusion-based molecular communication channel, an ISI Hamming code is proposed in which ISI characteristics are applied to a channel decoding algorithm. In order to prove the bit error rate performance of the proposed channel code, the bit error rate performance of the major channel codes applied to the molecular communication channel with ISI was compared and analyzed through simulation. From the simulation results, it can be seen that the bit error rate performance of the ISI Hamming code is the best when the number of radiated molecules is less than or equal to 1100. In addition, when the number of transmitted molecules is M=1000, the decoding method of the ISI Hamming code proposed in this paper has improved the bit error rate of approximately 5.9×10-5 compared to the Hamming code using only soft values. Compared with the ISI-mitigating channel code, which is effective for removing ISI in the molecular communication channel, the ISI Hamming code proposed in this paper is the most advantageous in a channel environment where the number of transmitted molecules is not big (M<1100). And we can see that the ISI-mitigating channel code is more advantageous when the number of transmitted molecules is large(M>1100).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1195-1201
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• 2005

This paper deals with procedures and results for teal time implementation of G.729 speech coder and channel coder including convolution codec, viterbi decoder, and interleaver using a fixed point DSP chip for radio communication systems. We described the method for real-time implementation based on integer simulation results and explained the implemented results by quality performance and required complexity for real-time operation. The required complexity was 24MIPS and 9MIPS in computational load, and 12K words and 4K words in execution code length for speech and channel. The functional evaluation was performed into two steps. The one was bit exact comparison with a fixed point C code, the other was executed by actual speech samples and error test vectors. Unlik other results such as individual implementation, We implemented speech and channel coders on a DSP chip with 160MIPS computation capability and 64 K words memory on chip. This results outweigh the conventional methods in the point of system complexity and implementation cost for radio communication system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.241-245
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• 2005

본 논문에서는 가변 전송율을 갖는 UWB 통신 시스템을 제안하고 다수의 무선 기기가 유동적으로 이동하는 파코넷 환경에서 다중접속 간섭 및 전송율에 따른 시스템 성능을 분석하였다. 또한, 전송품질을 향상시키기 위하여 Truncated Type-II Hyabrid ARQ 기법을 적용하여 불완전 채널 환경에서의 시스템 성능을 평가하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5A
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• pp.504-512
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• 2010

The paper proposes the 6bit 800MS/s flash A/D converter that can be applied to wireless USB chip-set. The paper simplified the error correction circuit and synchronization block as one circuit which are used respectively, and furthermore reduced the burden on the hardware. Comparing to the conventional error correction circuit, the proposed error correction circuit in this paper reduced 5 MOS transistors, the area of each error correction circuit is reduced by 9%. The A/D converter is fabricated with 0.18um CMOS 1-poly 6-metal process, and power dissipation is 182mW at 0.8Vpp input range and 1.8V supply voltage. The measured result shows 4.0bit of ENOB at 800MS/s conversion rate and 128.1MHz input frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1419-1424
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• 2005

This paper suggests a new cipher mode of operation which can recover cryptographic synchronization. First, we study the typical cipher modes of operation, especially focused on cryptographic synchronization problems. Then, we suggest a statistical cipher-feedback mode of operation. We define the error sources mathmatically and simulate propagation errors caused by a bit insertion or bit deletion. In the simulation, we compare the effects of changing the synchronization pattern length and feedback key length. After that, we analyze the simulation results with the calculated propagation errors. finally. we evaluate the performance of the statistical cipher-feedback mode of operation and recommand the implementation considerations.

• ETRI Journal
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• v.25 no.1
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• pp.19-24
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• 2003

This paper describes the performance of a Ku-band 5-bit monolithic phase shifter with metal semiconductor field effect transistor (MESFET) switches and the implementation of a ceramic packaged phase shifter for phase array antennas. Using compensation resistors reduced the insertion loss variation of the phase shifter. Measurement of the 5-bit phase shifter with a monolithic microwave integrated circuit demonstrated a phase error of less than $7.5{\circ}$ root-mean-square (RMS) and an insertion loss variation of less than 0.9 dB RMS for 13 to 15 GHz. For all 32 states of the developed 5-bit phase shifter, the insertion losses were $8.2{\pm}1.4$dB, the input return losses were higher than 7.7 dB, and the output return losses were higher than 6.8 dB for 13 to 15 GHz. The chip size of the 5- bit monolithic phase shifter with a digital circuit for controlling all five bits was 2.35 mm ${\times}$1.65 mm. The packaged phase shifter demonstrated a phase error of less than $11.3{\circ}$ RMS, measured insertion losses of 12.2 ${\pm}$2.2 dB, and an insertion loss variation of 1.0 dB RMS for 13 to 15 GHz. For all 32 states, the input return losses were higher than 5.0 dB and the output return losses were higher than 6.2 dB for 13 to 15 GHz. The size of the packaged phase shifter was 7.20 mm${\times}$ 6.20 mm.

• The Journal of the Acoustical Society of Korea
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• v.9 no.2
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• pp.61-69
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• 1990

We have investigated the digital bit synchronization problem in baseband communication receiver systems using the Gauss-Markov estimation technique which is equivalent to the weighted least square method. The realized bit synchronizer, including the data detector, processes the input signal two dimensionally into the transition phase and data level under the white Gaussian noise environment. We have confirmed the relization of the bit synchronizer via computer simulation. In addition, we have compared and evaluated the estimation error performance of the proposed method with that of the conventional DTTL method and of the minimum likelihood method.

• Journal of the Korean Institute of Telematics and Electronics
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• v.9 no.1
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• pp.25-30
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• 1972

Data Communication by sending pulse train and verifying the lock-in of a phase locked loop in receiving end is studied. The noise rejection property inherent to PLL is analysed. By using about six pulses in a train, data transimission rate of 20k bit/sec. in a telephone cable is achieved, thus permitting high speed data communication and an exellent immunity against noise.