• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.164-167
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• 2005

Recently, STC techniques have been considered to be candidate to support multimedia services in the next generation mobile radio communications and have been developed the many communications systems in order to achieve the high data rates. In this paper, we propose the Trellis-Coded Differential Space Time Modulation system with multiple symbol detection. The Trellis-code performs the set partition with unitary group codes. The Viterbi decoder containing new branch metrics is introduced in order to improve the bit error rate (BER) in the differential detection of the unitary differential space time modulation. Also, we describe the Viterbi algorithm in order to use this branch metrics. Our study shows that such a Viterbi decoder improves BER performance without sacrificing bandwidth and power efficiency.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.1-9
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• 2004

The important arithmetic operations over finite fields include exponentiation, division, and inversion. An exponentiation operation can be implemented using a series of squaring and multiplication operations using a binary method, while division and inversion can be performed by the iterative application of an AB$^2$ operation. Hence, it is important to develop a fast algorithm and efficient hardware for this operations. In this paper presents new bit-serial architectures for the simultaneous computation of multiplication and squaring operations, and the computation of an $AB^2$ operation over $GF(2^m)$ generated by an irreducible AOP of degree m. The proposed architectures offer a significant improvement in reducing the hardware complexity compared with previous architectures, and can also be used as a kernel circuit for exponentiation, division, and inversion architectures. Furthermore, since the Proposed architectures include regularity and modularity, they can be easily designed on VLSI hardware and used in IC cards.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.6 no.9
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• pp.81-90
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• 2016

Recently drones have become popular enough to be one of the hobby. The drone refers to an unmanned aerial vehicle which can fly and be steered by a radio wave without a pilot and it has a airplane or helicopter shape. The drone was first started to be used from military purpose, but its usage has been expanded to the private such as construction site, crop-dusting, field discovery, freight shipping and drones to prevent cheating. However the drone that we can see often in the market is expansive, hard to be repaired when it broken down and has a discomfort of the short flight time. In this paper, to solve an uncomfortable talk on the cheap 8-bits microcontrollers ATmega128 Using drone for implementation. Axes gyroscope and accelerometers mcu between posture an attitude control, communications through drone control, pid. Receiver input them into transmitter signals of movements to control drone c the programming was implemented in on the basis of language. drone using ATmega128 microcontroller is possible hovering, By utilizing a pin that are not required for control it can be used as a drone for a variety of uses.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.4
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• pp.47-52
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• 2009

The transmitted signal from a source is transmitted to a destination through wireless channels. But if the mobile destination is out of the coverage of the source or exists in the shady side of the coverage, the destination can not receiver the signal from the source and they can not maintain communication. In order to overcome these problems, we adopt relays. A system employing relays is a multi-hop relay system. In the multi-hop relay system, coverages of each relay that is used for different systems can overlap each other in some place. When there is a destination in this place, interference occurs at the destination. In this paper, we study on the efficient co-channel interference (CCI) cancellation algorithm. In the proposed strategy, CCI is mitigated by zero forcing (ZF) or minimum mean square error (MMSE) receivers. Moreover, successive interference cancellation (SIC) with optimal ordering algorithm is applied for rejecting CCI efficiently. And we analyzed and simulated the proposed system performance in Rayleigh fading channel. In order to justify the benefit of the proposed strategy, the overall system performance is illustrated in terms of bit error probability.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.5
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• pp.465-471
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• 2016

An IPTV has emerged as a widespread system when a realtime network and broadcasting system have progressed. Interestingly, it can also be organized with IPTV STBs and FC-AL for a high-quality TV content-sharing architecture. It is, however, not easy to configure a large community network with the FC-AL since it only has a 7-bit address space with supporting up to 127 users in the FC-AL single loop. We, therefore, propose an extendible FC-AL-based IPTV network architecture using a FC switch device. In this article, our suggested architecture shows a superb startup delay, such as less than 20msec. In addition, it demonstrates outstanding extendibility, such that the number of accomodable users increases almost linearly according to adding loops. Lastly, it reveals exceptional time-shifting hours, i. e., which supports more than 140 hours with 1000 users.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.9A
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• pp.784-789
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• 2011

In this paper, a precoder based on limited phase feedback is proposed to maximize user's receive signal-to-interference-plus-noise ratio (SINR) in coordinated multi-point (CoMP) coordinated scheduling / coordinated beamforming (CS/CB) precoding matrix indicator (PMI) scenario. Most conventional precoding techniques based on limited phase feedback have been considered in a single-cell environment. However, considering neighboring cells in a multi-cell environment, we enhance the conventional preocoding. method. First, to maximize receive SINR, precoding matrices are designed to maximize the serving cell's signal and to minimize the coordinated cells' signal. Also, a precoder which can be used in a limited bit feedback condition is suggested. Finally, the proposed precoder's performance is evaluated and compared with some other precoding techniques by using simulation under the CoMP CS/CB PMI scenario.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.925-931
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• 2008

In video coding standard H.264/AVC, variable block size mode algorithm improves compression efficiency but has need of a large amount of computation for various block modes and mode decision. Meanwhile, decided inter block modes depend on the complexity of a block image, and then the more complex a macroblock is, the smaller its block size is. This paper proposes fast inter block mode decision algorithm. It limits valid block modes to the block modes with a great chance for decision using the image complexity and carries out motion estimation rate-distortion optimization with only the valid block modes. In addition to that, it applies fast motion estimation PDE to the valid block modes with only the $16{\times}16$ block mode. The reference software JM 9.5 was executed to estimate the proposed algorithm's performance. The simulation results showed that the proposed algorithm could save about 24.12% of the averaged motion estimation time while keeping the image quality and the bit rate to be -0.02dB and -0.12% on the average, respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.6
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• pp.673-679
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• 2014

The important requirements of designing a pattern classifier are high throughput and low memory requirements, and low cost hardware implementation. A pattern classifier by using Multiple Attractor Cellular Automata(MACA) proposed by Maji et al. reduced the complexity of the classification algorithm from $O(n^3)$ to O(n) by using Dependency Vector(DV) and Dependency String(DS). In this paper, we generate a pattern classifier using LFSR to improve efficiently the space and time complexity and we propose a method for finding DV by using the 0-basic path. Also we investigate DV and the attractor of the generated pattern classifier. We can divide an n-bit DS by m number of $DV_i$ s and generate various pattern classifiers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.9
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• pp.721-727
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• 2012

Since a conventional multi-cell transmit diversity scheme depends on the feedback from the user for the channel gain information, its performance gets to severely degrade when the channel varies fast due to the high mobility of the user. Also, transmit power of the base station cannot be fully used in the conventional scheme because only one transmit antenna is used for data transmission. In this paper, we propose a multi-cell transmit diversity scheme appropriate for fast fading channel. In the proposed scheme, channel-independent precoding vector is applied over all transmit antennas and different precoding vectors are applied for neighboring subcarriers so that the received signal is avoided to experience deep fading over multiple neighboring subcarriers. Simulation results show that the proposed scheme has better detector output signal-to-noise ratio (SNR) and bit error rate (BER) performances than the conventional scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.58-70
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• 1990

This paper describes a VLSI implementation of real-time two dimensional DCT processor for the subprimary rate video codec system. The proposed architecture exploits the parallelism and concurrency of the distributes architecture for vector inner product operation of DCT and meets the CCITT performance requirements of video codec for full CSIF 30 frames/sec. It is also shown that this architecture satisfies all the CCITT IDCT accuracy specification by simulating the suggested architecture in bit level. The efficient VLSI disign methodology to design suggested architecture is considered and the module generator oriented design environments are constructed based on SUN 3/150C workstation. Using the constructed design environments. the suggensted architecture have been designed by double metal 2micron CMOS technology. The chip area fo designed 8x8 2-D DA-DCT (Distributed Arithmetic DCT) processor is about 3.9mmx4.8mm.