• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.565-570
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• 2012

This paper has proposed a multi-channel low pass filter (LPF) for LTE-Advanced systems. The proposed LPF is an active-RC 5th chebyshev topology with three cut-off frequencies of 5 MHz, 10 MHz, and 40 MHz. A 3-bit tuning circuit has been adopted to prevent variations of each cut-off frequency from process, voltage, and temperature (PVT). To achieve a high cut-off frequency of 40 MHz, an operational amplifier used in the proposed filter has employed a PMOS cross-connection load with a negative impedance. A proposed filter has been implemented in a 0.13-${\mu}m$ CMOS technology and consumes 20.2 mW with a 1.2 V supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1735-1740
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• 2005

SoC design integrates many IPs that operate at different frequencies and the use of the different clock for each IP makes the design the most effective one. An asynchronous FIFO is required as a kind of a buffer to connect IPs that are asynchronous. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, an asynchronous FIFO is designed to transfer data across asynchronous clock domains by using a valid bit scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the Bate level to compare with other FIFO scheme. The subject mater of this paper is under patent pending.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.491-494
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• 2005

In this paper, a QT_rev protocol is proposed for identifying all the tags within the identification range. The proposed QT_rev protocol revises the QT protocol, which has a memoryless property. In the QT_rev protocol, the tag will send the remaining bits of their identification codes when the query string matches the first bits of their identification codes. After the reader receives all the responses of the tags, it knows which bit is collided. If the collision occurs in the last bit, the reader can identify two tags simultaneously without further query.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.820-822
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• 2005

We have designed a 32-bit microprocessor with fixed point digital signal processing functionality. This processor, combines both general-purpose microprocessor and digital signal processor functionality using the reduced instruction set computer design principles. It has functional units for arithmetic operation, digital signal processing and memory access. They operate in parallel in order to remove stall cycles after DSP or load/store instructions, which usually need one or more issue latency cycles in addition to the first issue cycle. High performance was achieved with these parallel functional units while adopting a sophisticated five-stage pipeline stucture.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.154-157
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• 2004

A realization for the wireless transmission system on the Un image using embedded server is presented on the paper to be simply to omni-direction data acquisition. The embedded system is composed of the image data acquisition which has CMOS sensor and lame grabber, the embedded server that takes the wireless LAN target board, and client part that is monitoring the image from the embedded server. The experiment result is average 12.7fps in 8bit on the 320$\times$240, 4:2:2 YCbCr. The system enable images transmission to be soft . monitoring.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.6B
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• pp.1068-1073
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• 2000

In this paper, we propose a serially concatenated turbo bode/turbo equalizer scheme for optical storage systems. Without modulation coding, a random data sequence is directly passed through the optical channel. In simulation, the channel includes jitter of 15% and AWGN. The densities of the channel are S=4.6 and S=7.0. The code rates of turbo code are 4/5, 8/9 and 16/17. All code rates, the bit error probability is less than 10-5 at 24dB when we and jitter of 15%.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.9-12
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• 2001

본 논문에서는 유럽 통신 표준화기구인 ETSI 의 SMGll에서 채택된 GSM Full Rate(FR) 보코더 알고리wma[1]을 Teak DSP Core를 이용하여 실시간 구현하였다. GSM FR 보코더는 유럽에서 사용하는 통신 시스템인 GSM 의 full-rate Traffic Channel(TCH)의 표준 코덱[2]으로서 GSM HR, GSM EFR GSM AMR과 더불어 모뎀칩 내에 장착되는 필수적인 음성 서비스이다. 구현된 GSM FR는 13.05kbps의 비트율을 가지고 있으며, 인코더와 디코더 기능 외에 voice activity detection(VAD)[3]블록과 DTX[4]블록 등의 부가 기능도 구현되어 있다. 구현에 사용된 Teak[5]는 DSP Group 의 16bit고정 소수점 DSP core로서 최대 140MIPS 의 성능을 낼 수 있고 400bits ALU 와 두개의 MAC 이 장착되어 있어 음성 및 채널 부호화기의 실시간 처리에 최적화 되어있다. 구현된 GSM FR 은 인코더와 디코더 부분이 각각 약 235 MIPS 및 1.19MIPS 의 복잡도를 나타내며, 사용된 메모리는 프로그램 ROM 3.9K words, 데이터 ROM(table) 396 words 및 RAM 932words이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.9
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• pp.792-797
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• 2013

This paper has derived the conversion loss according to the synchronized condition between the transmitted and locally generated spreading signals for the civil global positioning system (GPS) receiver in the heavy wideband Gaussian noise environments. From this, the outputs of the 2-bit nonuniform quantizer, which has the minimum conversion loss, is set to ${\pm}1$ and ${\pm}2$, while the quantization step size is approximated to the jamming-to-signal power ratio.

• Journal of Internet Computing and Services
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• v.3 no.5
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• pp.9-17
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• 2002

CSIX-L1 is the Common Switch Interface that defines a physical interface for transferring information between a traffic manager (Network Processor) and a switching fabric in ATM, IP, MPLS, Ethernet and data communication areas. In Tx, data to be transmitted is generated in Cframe which is the base information unit and in Rx, original data is extracted from the received Cframe. CSIX-L1 suppots the 32, 64, 96, and 123-bit interface and generates a variable length CFrame and Idle Cframe. Also CSIX-L1 appends Padding byte and supports 16-bit Vertical parity, CSIX-L1 is designed using Xilinx 4,1i. After functional and timing simulations are completed. CSIX-L1 module is downloaded in Xilinx FPGA XCV1000EHQ240C and verified. The synthesized CSIX module operates at 27MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9A
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• pp.931-939
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• 2007

This paper describes the system which automatically generates instruction-set simulators cores using the SMDL. SMDL describes structure and instruction-set information of a target DSP machine. Analyzing behavioral information of each pipeline stage of all instructions on a target ASIPS, the proposed system automatically generates a cycle-accurate instruction set simulator in C++ for a target processor. The proposed system has been tested by generating instruction-set simulators for ARM9E-S, ADSP-TS20x, and TMS320C2x architectures. Experiments were performed by checking the functions of the $4{\times}4$ matrix multiplication, 16-bit IIR filter, 32-bit multiplication, and the FFT using the generated simulators. Experimental results show the functional accuracy of the generated simulators.