• Journal of KIISE:Computer Systems and Theory
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• v.26 no.8
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• pp.918-929
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• 1999

동기식 스트림 암호통신 방식을 사용하는 암호통신에서는 암/복호화 과정 수행시 암호통신 과정에서 발생하는 사이클슬립으로 인해 키수열의 동기이탈 현상이 발생되고 이로 인해 오복호된 데이타를 얻게된다. 이러한 위험성을 감소하기 위한 방안으로 현재까지 암호문에 동기신호와 세션키를 주기적으로 삽입하여 동기를 이루는 주기적인 동기암호 통신방식을 사용하여 왔다. 본 논문에서는 CDMA(Cellular Division Multiple Access) 이동망에서 데이타서비스를 제공할 때 사용되는 점대점 프로토콜의 주소영역의 특성을 이용하여 단위 측정시간 동안 측정된 주소비트 정보와 플래그 패턴의 수신률을 이용하여 문턱 값보다 작은경우 동기신호와 세션키를 전송하는 비주기적인 동기방식을 사용하므로써 종래의 주기적인 동기방식으로 인한 전송효율성 저하와 주기적인 상이한 세션키 발생 및 다음 주기까지의 동기이탈 상태의 지속으로 인한 오류확산 등의 단점을 해결하였다. 제안된 알고리즘을 링크계층의 점대점 프로토콜(Point to Point Protocol)을 사용하는 CDMA 이동망에서 동기식 스트림 암호 통신방식에 적용시 동기이탈율 10-7의 환경에서 주기가 1sec인 주기적인 동기방식에서 요구되는 6.45x107비트에 비해 3.84x105비트가 소요됨으로써 전송율측면에서의 성능향상과 오복호율과 오복호 데이타 비트측면에서 성능향상을 얻었다. Abstract In the cipher system using the synchronous stream cipher system, encryption / decryption cause the synchronization loss (of key arrangement) by cycle slip, then it makes incorrect decrypted data. To lessen the risk, we have used a periodic synchronous cipher system which achieve synchronization at fixed timesteps by inserting synchronization signal and session key. In this paper, we solved the problem(fault) like the transfer efficiency drops by a periodic synchronous method, the periodic generations of different session key, and the incorrectness increases by continuing synchronization loss in next time step. They are achieved by the transfer of a non-periodic synchronous signal which carries synchronous signal and session key when it is less than the threshold value, analyzing the address field of point-to-point protocol, using the receiving rate of address bits information and flag patterns in the decision duration, in providing data services by CDMA mobile network. When the proposed algorithm is applied to the synchronous stream cipher system using point-to-point protocol, which is used data link level in CDMA mobile network, it has advanced the result in Rerror and Derror and in transmission rate, by the use of 3.84$\times$105bits, not 6.45$\times$107bits required in periodic synchronous method, having lsec time step, in slip rate 10-7.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.7
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• pp.1055-1061
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• 2002

This paper deals with a design and fabrication of an electronic ballast for 70[W] ceramic discharge metal halide lamps. The proposed ballast is composed of a rectifier, an active power factor correction circuit (PFC), a half-bridge inverter, a LC resonant circuit and a microprocessor. The developed ballast also includes a specially designed time circuit which provides reignition signal of lamps. Running frequency of the ballast is .jet at 40[kHz] to avoid acoustic-resonance and flickering. From the experimental results, input power factor and efficiency of the ballast are estimated 99.8[%] and 93.1[%], respectively.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.27-34
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• 2010

This paper presents a methodology for classifying left and right motor imagery using a neural network with weighted fuzzy membership functions (NEWFM) and wavelet-based feature extraction. Wavelet coefficients are extracted from electroencephalogram(EEG) signal by wavelet transforms in the first step. In the second step, sixty numbers of initial features are extracted from wavelet coefficients by the frequency distribution and the amount of variability in frequency distribution. The distributed non-overlap area measurement method selects the minimized number of features by removing the worst input features one by one, and then minimized six numbers of features are selected with the highest performance result. The proposed methodology shows that accuracy rate is 86.43% with six numbers of features.

• The Transactions of the Korea Information Processing Society
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• v.6 no.7
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• pp.1919-1928
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• 1999

There are no standard language for the specification of speed-independent circuits because existing specification methods are designed appropriately to each synthesis methodology. This paper suggests a method of using VHDL, a standard hardware description language, for the specification and synthesis of speed-independent circuits. Because VHDL is a multi-purpose language, we define a subset of VHDL which can be used for the synthesis. We transform the VHDL description into a signal transition graph and then synthesize speed-independent circuits by using a previous synthesis algorithm which uses a signal transition graph as the specification method. We suggest a systematic transformation method which transforms each VHDL statement into a partial signal transition graph and then merges them into a signal transition graph. This work is a step towards to the development of an integrated framework in which we can utilizes the existing CAD tools based on VHDL. Also, this work will enable a easier migration of the current circuit designers into asynchronous circuit design.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.4
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• pp.1-6
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• 2003

In this Paper, the moving image is detected by a collision preventive system. The noise of these images is reduced by a mean filter. In case of detecting a movement with a binary difference image the moving area is detected exactly by the labeling and the projective method. When the image move slowly with the tracking mode of the system, the center of the tracking window move to the previous tracking window. And the tracking windows are divided into a tracking mode and a coasting mode which are determine by the Contrast-Difference Correlation of the date obtained from a difference image. The coasting mode determine whether continue the tracking step or not comparing the coasting-time values to reducing the error by the disturbance. The coasting and tracking of these moving images are verified by the result of the simulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.6
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• pp.994-1001
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• 2001

In this paper, we propose the Improved SIR-based Power Control method in mobile communication system. Generally speaking, SIR-based design considering both channel noise and multiuser interference is accurate indication of signal quality and provides good performance. However, one serious problem associated with SIR-based Power Control is the potential of Positive Feedback which can endanger the stability of the system. Therefore from SIR definition, we decrease the signal\`s Interference we will got a improved SIR and have a stable power control Also in mobile using window register which has Up-Maintain-Down power control step size instead of Up-Down, we got a better performance. This paper assesses the performance of Improved SIR based Power Control using PIC and window register. The proposed Improved SIR based Power Control is presented and compared with existing SIR based Power Control and Strength-and-SIR based Power Control.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.293-298
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• 2006

Thermopiezoelectric method, using poly silicon heater and a piezoelectric sensor, was proposed for writing and reading in a probe based data storage system. Resistively heated tip writes data bits while scanning over a polymer media and piezoelectric sensor reads data bits from the self-generated charges induced by the deflection of the cantilever. 34${\times}$34 array of thermopiezoelectric nitride cantilevers were fabricated by a single step wafer level transfer method. We analyzed the noise level of the charge amplifier and measured the noise signal. With the sensor and the charge amplifier 20mn of deflection could be detected at a frequency of 10KHz. Reading signal was obtained from the cantilever array and the sensitivity was calculated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.446-455
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• 2001

In this paper, the precise synchronized clock generator using GPS receiver is presented. The GPS receiver provides a synchronized IPPS signal which guaranties a reliable standard time mark. This signal allows us to do time synchronization and correct the time step. We designed and implemented the precise synchronized clock generator based on DPLL in order to generate a high-resolution clock from a low-cost inaccurate oscillator with ALTERA FLEX EPM6016TC144-3. We also implemented a hardware unit and proved that the unit provides 1MHz clock output which had a high resolution and accuracy when it was combined with GPS receiver.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.10
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• pp.1045-1053
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• 2009

Precision stages for 6-DOF positioning, actuated by PZT stacks, which are fed back by gap sensors and guided by flexure hinges, have enlarged their application territory in micro/nano manufacturing and measurement area. The precision stages inherently have such limitations as the nonlinearity between input and output in piezoelectric stacks, feedback signal noise in precision capacitive gap sensors and low material damping in precision kinematic linkages of mechanical flexures. To surmount these limitations, the precision stage is modeled with physics-based variables, which are identified by transient response correspondence, and a gain margin calculation algorithm using the Prandtl-Ishlinskii model and describing function is newly developed to assess system performance more precisely than linear controller design schemes. Based on such analyses, a precision positioning controller is designed. Excellent positioning accuracy with rapid settlement accomplished by the controller is shown in step responses of the closed-loop system.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.