• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.712-720
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• 2001

Algorithms from the research of the layout migration were proposed in the paper. These are automatic recognition algorithm for the VLSI devices from it, graph based construction algorithm to maintain the constraints, dependencies, and design rule between the devices, and high speed compaction algorithm to reduce size of the VLSI area and reuse the design with compacted size for the new technology. Also, this paper describes that why proposed algorithms are essential for the era of the SoC (System on a Chip), design reuse, and IP DB, which are the big concerns in these days. In addition to introduce our algorithms, the benchmark showed that our performance is superior by 27 times faster than that of the commercial one, and has better efficiency by 3 times in disk usage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.454-464
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• 2002

In the ATM-PON (Asynchronous Transfer Mode-Passive Optical Network), the downstream cell transmitted by an OLT is broadcast to all ONUs. The ONU receives selectively its own cells by VP filtering. On the other hand, the upstream cell can be transmitted by ONU in the case of receiving a grant from the OLT. After providing the grant to an ONU, the OLT expects the arrival of a cell after an elapse of the equalized round trip delay. ITU-T G.983.1 recommends that one bit error is allowed between the expected arrival time and the actual arrival time at the OLT. Because the ONU processes the different delay to each type of grant (ranging, user cell, and mimi-slot grant), it is not simple to design the transmission part of ONU. In this paper, we implement a grant processor which provides the delay accurately in the ONU TC chip with the FPGA. For the given equalized delay, it deals with the delay for the cell, the byte, and the bit unit by using the shift register, the byte counter, and the D flip-flop, respectively. We verify the operation of the grant processor by the time simulation and the measurement of the optical board output.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.5
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• pp.919-929
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• 2013

Recently, a variety of IT technologies are applied to the vehicle. However, some vehicle-IT technologies without security considerations may cause security problems. Specially, some researches about a smart key system applied to automobiles for authentication show that the system is insecure from replay attacks and modification attacks using a wireless signal of the smart key. Thus, in this paper, we propose an authentication method for the driver by using driving patterns. Nowadays, we can obtain driving patterns using the In-vehicle network data. In our authentication model, we make driving ppatterns of car owner using standard normal distribution and apply these patterns to driver authentication. To validate our model, we perform an k-fold cross validation test using In-vehicle network data and obtain the result(true positive rate 0.7/false positive rate is 0.35). Considering to our result, it turns out that our model is more secure than existing 'what you have' authentication models such as the smart key if the authentication result is sent to the car owner through mobile networks.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.1
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• pp.47-56
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• 2012

Bicycle has a large amount of kinetic energy available for energy harvesting technology in its speedy and balanced riding movement. Systematic and realistic analysis of its dynamic property is essential to improve the efficiency of energy harvester. However, there has not been enough researches about precise measurement or analysis of bicycle dynamics on real roads. This study aims to investigate the characteristics of vibrational movement of bicycle using MEMS-based accelerometer and to develop a prototype of electromagnetic energy harvester with nonlinear behavior which is proper to the random vibrations accompanied in bicycle riding. The vibrational components have average magnitude of 1 g and turn out to be independent of riding speed. The developed prototype of energy harvester was installed on a front port of a bicycle to use this ambient vibration and generated an average electrical power of 1.5 mW which is enough to support power for most of portable sensors and short range radio-frequency communication. Further study about isolation of vibration from a rider and conversion efficiency is ongoing. The developed energy harvester is expected to be a platform technology for sustainable portable power supply for various smart IT devices and applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• Korean Journal of Heritage: History & Science
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• v.56 no.2
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• pp.246-262
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• 2023

This study analyzed policy implementation factors focusing on how Donuimun, a demolished cultural heritage, was digitally restored and the policy implementation process of Donuimun Gate restoration. Through this, the characteristics of the implementation process of the digital Donuimun Gate restoration policy promoted by public-private multilateral collaboration were examined and implications were sought for how institutions with different interests solved problems and collaborated in the implementation process. The research method was focused on policy implementation factors including policy executive factors, policy content factors, policy resource factors, and policy environment factors, and the process was analyzed for each detailed component. Along with literature analysis, in-depth interviews were conducted with participants in policy implementation. As a result of the study, first, it was found in the policy executive factor that the quick decision-making leadership of the policy manager and the flexible attitude of the person in charge of the government agency had a positive effect on preventing conflicts between different interest groups. Second, in terms of policy content, establishing a common goal that everyone can accept and moving forward consistently gave trust and created synergy. Third, in the policy implementation resource factor, the importance of the budget was emphasized. Finally, as an environmental factor for policy implementation, the opening of 5G mobile communication for the first time along with the emergence of the Fourth Industrial Revolution at the time of policy implementation acted as a timely factor. The digital Donuimun Gate was the first case of restoring a lost cultural heritage with AR and VR, and received attention and support from the mass media and the public. This also shows that digital restoration can be a model case that can be a solution without conflicts with local residents where cultural heritages are located or conflicts between stakeholders in the preservation and restoration of real objects.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.9 no.5
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• pp.49-58
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• 2010

The traffic signal controllers being used in the domestic currently are being manufactured based on the korean national police standard which was developed for controlling the quad-light traffic signal having the red, yellow, left-turn arrow, and green lights. But according to the national policy for the traffic operation, they have to be changed to be able to switch the tri-light signal having red, yellow and green lights. In this study, a new tri-light traffic signal controller was designed and developed by the way improving the Signal Control Unit of the existing quad-light standard traffic controller. The Load Signal Unit(LSU) was improved to output 6 signals which are the two assemblies of three signal indications having the red, yellow, and green lights. To enough traffic signals output to control each directional movements and the various transport modes which are car, bus, bike, and pedestrian etc., the connector bus system was designed to be able to accommodate maximum 96 signals outputs being constructed by 16 LSUs. Flasher device was developed to be able to support maximum 32 red signals. In the software, the communication protocol between traffic control center and the traffic signal controller was improved and new signal map code values were defined for the developed LSU controlling the quad-light traffic signal. A model of the quad-light traffic signal controller developed and was tested three operations, protocol-operation, remote-command and control-mode. The test result operated all of them successfully.