• Journal of Korea Society of Industrial Information Systems
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• v.12 no.4
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• pp.119-125
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• 2007

In this paper, a miniaturized PCB-integrated antenna is proposed for bluetooth applications. The proposed antenna is a modified form of the printed inverted F antenna where the size reduction is achieved by employing the meander strip for the resonant length part of the radiator. The antenna dimension is optimized using the commercial electromagnetic software MWSTM. The designed antenna is fabricated by the standard photo-etching technique and its performance is measured. The fabricated antenna shows a bandwidth of 125MHz centered at 2.45GHz and a gail of -0.23dBi. The size of the proposed antenna is $9.65mm{\times}5.95mm$ corresponding to the 55 percent of the area of the existing printed inverted F antenna.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.59-64
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• 2002

In the RFID system using ISM-band, The tag mounted at the object has used the DC power by rectifying the RF signals of the small antenna for operating the micro-controller and memory. The performance of the tag would be reduced because of the second harmonics generated by the nonlinearity of the semiconductor and the spurious signal excited the high order mode of the antenna. This paper has realized the novel type low-pass filter with "the Stub-I type DGS slot structure" to improve the efficiency of the tag by suppressing the harmonics. The optimized frequency character at the pass-band/stop-band has obtained by tuning the stub width and slit width of I type slot. The measured result of the LPF has the cutoff frequency 3.25 GHz, the insertion loss about -0.29~-0.3 dB at pass-band 2.4 GHz~2.5 GHz, the return loss about -27.688~-33.665 dB at pass-band with a good performance, and the suppression character is about -19.367 dB at second harmonics frequency 4.9 GHz. This DGS LPF may be applied the various application as the RFID, WLAN to improve the efficiency of the system by suppressing the harmonics and spurious signals. 

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.5
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• pp.249-254
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• 2014

In this paper, minimizing of a parabolic edge planar monopole antenna by scaling method is presented. With the aid of a matching step and discontinuous CPW, the antenna easily adjusts the impedance matching. We used an FR4 dielectric substrate with a dielectric constant of 4.4. The dimensions of the antenna are $26mm{\times}31mm{\times}1.6mm$. A return loss value of more than 10dB was found in the 2.37GHz to 10.52GHz (8.15GHz) range of the antenna fed by the discontinuous CPW. The radiation pattern is about the same as that of the dipole antenna at all frequencies. Configuration elements of the antenna except feed part were reduced into the same rate. So, the size of the antenna was decreased and a broadband property was maintained. Therefore, the self-complementary characteristic of the antenna was confirmed. While satisfying the UWB band, having the smallest size in the antenna miniaturized by scaling;when scale was 0.6. The dimensions of the antenna are $15.6mm{\times}18.6mm{\times}1.6mm$. The return loss was more than 10 dB of the measured result in the range of 3.07GHz to 12.59GHz (9.52GHz).

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.174-179
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• 2013

This paper presents a capacitor loaded tunable bandpass chip filter using multiple split ring resonators (MSRRs) with two transmission zeros. To obtain high selectivity and minimize the chip size, asymmetric feed lines are adopted to make a pair of transmission zeros located on each side of passband. Compared with conventional filters using cross-coupling or source-load coupling techniques, the proposed filter uses only two resonators to achieve high selectivity through a pair of transmission zeros. In order to optimize selectivity and sensitivity (insertion loss) of the filter, the effect of the position of asymmetric feed line on transmission zeros and insertion loss is analyzed. The SOI-CMOS switched capacitor composed of metal-insulator-metal (MIM) capacitor and stacked-FETs is loaded at outer rings of MSRRs to tune passband frequency and handle high power signal up to +30 dBm. By turning on or off the gate of the transistors, the passband frequency can be shifted from 4GH to 5GHz. The proposed on-chip filter is implemented in 0.18-${\mu}m$ SOI CMOS technology that makes it possible to integrate high-Q passive devices and stacked-FETs. The designed filter shows miniaturized size of only $4mm{\times}2mm$ (i.e., $0.177{\lambda}g{\times}0.088{\lambda}g$), where ${\lambda}g$ denotes the guided wave length of the $50{\Omega}$ microstrip line at center frequency. The measured insertion loss (S21)is about 5.1dB and 6.9dB at 5.4GHz and 4.5GHz, respectively. The designed filter shows out-of-band rejection greater than 20dB at 500MHz offset from center frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.17-22
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• 2006

CMOS LC VCO with fast response adaptive frequency calibration (AFC) technique for IEEE 802.11a/b/g WLANs is designed in 1.8V $0.18{\mu}m$ CMOS process. The possible operation is verified for 5.8GHz band, 5.2GHz band, and 2.4GHz band using the switchable L-C resonators. To linearize its frequency-voltage gain (Kvco), optimized multiple MOS varactor biasing tecknique is used. In order to operate in each band frequency range with reduced VCO gain, 4-bit digitally controlled switched- capacitor bank is used and a wide-range digital logic quadricorrelator (WDLQ) is implemented for fast frequency detector.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.484-494
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• 2014

We describe a digitally controlled oscillator (DCO) which compensates the frequency variations for process, voltage, and temperature (PVT) variations with an accuracy of ${\pm}2.6%$ at 2.5 GHz. The DCO includes an 8 phase current-controlled ring oscillator, a digitally controlled current source (DCCS), a process and temperature (PT)-counteracting voltage regulator, and a bias current generator. The DCO operates at a center frequency of 2.5 GHz with a wide tuning range of 2.2 GHz to 3.0 GHz. At 2.8 GHz, the DCO achieves a phase noise of -112 dBc/Hz at 10 MHz offset. When it is implemented in an all-digital phase-locked loop (ADPLL), the ADPLL exhibits an RMS jitter of 8.9 ps and a peak to peak jitter of 77.5 ps. The proposed DCO and ADPLL are fabricated in 65 nm CMOS technology with supply voltages of 2.5 V and 1.0 V, respectively.

• Journal of the Korean Magnetics Society
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• v.9 no.1
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• pp.7-16
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• 1999

Stoichiometric and nonstoichiometric $Y_{3-x}Fe_{5+x}O_{12})$ polycrystalline samples (x=0.00, 0.05, 0.10, 0.30, -0.05, -0.10, -0.30) were prepared by solid state reaction method. The magnetic properties of the sample were investigated by FMR (ferromagnetic resonance) technique at microwave frequency 5.11 GHz (G-band) and 23.39 GHz (K-band) respectively. The spectroscopic splitting factor g were estimated to be 2.04~2.35 from the derivative absorption lines. As the samples became yttrium $(Y^{3+})$ excess and iron $(Fe^{3+})$ excess, Magnetizations were decreased. But resonance linewidth were increased. To investigate the anisotropy, the angular dependence of resonance magnetic fields were measured. Angular dependence of effective magnetizations were measured by FMR from 77 K to 300 K at K-band microwave frequency (23.39 GHz) and the saturation magnetizations were measured by VSM. The Bloch coefficients B and C were determined by fitting. $M_{eff}(0)$ was obtained by the extrapolation from 80 K. From this result, the spin wave stiffness constant D $(about\; 162~206 \;eV{\AA}^2)$and average square range of exchange interaction $$$(about \;5.84~12.13\;{\AA}^2)$ were determined.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.1-9
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• 2006

In this paper, a couple of 10Gb/s transimpedance amplifiers are realized in a 0.18um standard CMOS technology for optical communication applications. First, the voltage-mode inverter TIA(I-TIA) exploits inverter input configuration to achieve larger effective gm, thus reducing the input impedance and increasing the bandwidth. I-TIA demonstrates $56dB{\Omega}$ transimpedance gain, 14GHz bandwidth for 0.25pF photodiode capacitance, and -16.5dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. However, both its inherent parasitic capacitance and the package parasitics deteriorate the bandwidth significantly, thus mandating very judicious circuit design. Meanwhile, the current-mode RGC TIA incorporates the regulated cascade input configuration, and thus isolates the large input parasitic capacitance from the bandwidth determination more effectively than the voltage-mode TIA. Also, the parasitic components give much less impact on its bandwidth. RGC TIA provides $60dB{\Omega}$ transimpedance gain, 10GHz bandwidth for 0.25pF photodiode capacitance, and -15.7dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. Main drawback is the power dissipation which is 4.5 times larger than the I-TIA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.59-60
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• 2018

In this paper, we studied a design method for a band-pass waveguide filter with a modified H-type resonant iris (RI) placed in a thin transverse wall of a rectangular waveguide. The horizontal straight gap at the center of a conventional H-shaped iris is modified to a U-shaped one to increase the equivalent capacitance, and the equivalent inductance is improved by changing the vertical two straight slots into C-shaped ones. A third-order band pass filter using the proposed modified H-shaped iris was designed and, it was observed that the filter operated in the frequency range of 9.22-9.75 GHz with its insertion loss of 0.5 dB and return loss of 17 dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.2
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• pp.262-265
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• 2012

In this paper, a Ka-band 8 W power amplifier module with WR-28 waveguide input and output ports is implemented and measured using four 2 W power amplifier modules and 4:1 waveguide power combiners with high isolation of 25 dB at 35 GHz. The 2 W power amplifier modules are fabricated using waveguide-to-microstrip transitions and show output power of 32.5~33.3 dBm and power gain of 26.9~28.7 dB at 35 GHz. Four 2 W power amplifier modules are combined through 4:1 waveguide power combiners with resistive septum and the combined power shows 39.0 dBm(8 W) under 6 V drain bias and 39.6 dBm(9.1 W) under 6.5 V drain bias at 35 GHz.