• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.5
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• pp.845-852
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• 2024

In this paper, we propose mult-band antenna included Sub-6 GHz band for WLAN system. The proposed antenna has the fourth strip line and slot in the partial ground plane to obtain impedance matching. The total substrate size is 48.0 mm (W)×50.0 mm (L), thickness (h) 1.0 mm, and the dielectric constant is 4.4, which is made of 26.0 mm (W2)×42.0 mm (L1+L2+4.0(L1+L2+4.0 mm+L8+L9) antenna size on the FR-4 substrate. From the fabrication and measurement results, bandwidths of 115 MHz (0.825 to 0.940 GHz) for 900 MHz band, 210.0 MHz (2.29 to 2.50 GHz) for 2.4 GHz band, 270.0 MHz (3.45 to 3.72 GHz) for 3.5 GHz band, and 930.0 MHz (4.95 to 5.88 GHz) for 5.0 GHz band were obtained on the basis of -10 dB. Also, gain and radiation pattern characteristics are measured and shown in the frequency triple band as required.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.1
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• pp.137-146
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• 2009

We present a micromechanical digital-to-analog (DA) variable capacitor using a parallel digital actuator array, capable of accomplishing high-Q tuning. The present DA variable capacitor uses a parallel interconnection of digital actuators, thus achieving a low resistive structure. Based on the criteria for capacitance range ($0.348{\sim}1.932$ pF) and the actuation voltage (25 V), the present parallel DA variable capacitor is estimated to have a quality factor 2.0 times higher than the previous serial-parallel DA variable capacitor. In the experimental study, the parallel DA variable capacitor changes the total capacitance from 2.268 to 3.973 pF (0.5 GHz), 2.384 to 4.197 pF (1.0 GHz), and 2.773 to 4.826 pF (2.5 GHz), thus achieving tuning ratios of 75.2%, 76.1%, and 74.0%, respectively. The capacitance precisions are measured to be $6.16{\pm}4.24$ fF (0.5 GHz), $7.42{\pm}5.48$ fF (1.0 GHz), and $9.56{\pm}5.63$ fF (2.5 GHz). The parallel DA variable capacitor shows the total resistance of $2.97{\pm}0.29\;{\Omega}$ (0.5 GHz), $3.01{\pm}0.42\;{\Omega}$ (1.0 GHz), and $4.32{\pm}0.66\;{\Omega}$ (2.5 GHz), resulting in high quality factors which are measured to be $33.7{\pm}7.8$ (0.5 GHz), $18.5{\pm}4.9$ (1.0 GHz), and $4.3{\pm}1.4$ (2.5 GHz) for large capacitance values ($2.268{\sim}4.826$ pF). We experimentally verify the high-Q tuning capability of the present parallel DA variable capacitor, while achieving high-precision capacitance adjustments.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.5
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• pp.453-458
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• 2010

In this work, a 18 GHz divide-by-4 injection-locked frequency divider(ILFD) based on ring oscillator has been developed in $0.13-{\mu}m$ Si RFCMOS technology. The free-running oscillation frequency is from 4.98 to 5.22 GHz and output power is about －30 dBm, consuming 33.4 mW with a 1.5 V supply voltage. At 0 dBm input power, the locking range is 3.5 GHz(17.75~21.25 GHz) and with varactor tuning, the operating range is increased up to 5.25 GHz(16.0~21.25 GHz). The fabricated chip size is $0.76\;mm{\times}0.57\;mm$ including DC and RF pad.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.8
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• pp.42-50
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• 2007

This paper presents design methods for dual-frequency(2.4/5.8GHz) active receiving antennas. The proposed active receiving antennas are designed to interconnect the output port of a wideband antenna to the input port of an active device of High Electron Mobility Transistor directly and to receive RF signals of 2.4GHz and 5.2GHz simultaneously where the impedance matching conditions are optimized by adjusting the length of $1/20{\lambda}_0$(@5.8GHz) CPW transmission line in the planar antenna The bandwidth of implemented dual-frequency active receiving antennas is measured in the range of 2.0GHz to 3.1GHz and 5.25GHz to 5.9GHz. Gains are measured of 17.0dB at 2.4GHz and 15.0dB at 5.2GHz. The measured noise figure is 1.5dB at operating frequencies.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.8-14
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• 2016

In this paper, a compact CPW-fed antenna for 5 GHz (5.15-5.35 GHz, 5.725-5.825 GHz) band WLAN applications is presented. The designed antenna's shape is step structure. The antenna is fabricated and measured into FR-4 substrate of dielectric comstant 4.2 and thickness 1.0 mm with optimized parameters obtained by simulation. We confirm that it is operated as antenna for WLAN applications by obtaining the measured return loss level of < -10 dB in 5.133-5.982 GHz. The dimensions of the antenna ($20.0{\times}16.0{\times}1.0mm^3$) shows an compactness of about 67.17% with respect to a conventional folded slot antenna.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.8
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• pp.819-826
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• 2002

In this paper, the performance of Au / $Ba_{0.5}Sr_{0.5}TiO_3$ (BST) / Magnesium oxide (MgO) two-layered electrically tunable band-pass Filters (BPFs) is demonstrated. The devices consist of microstrip, coplanar waveguide (CPW), and conductor-backed coplanar waveguide (CBCPW) structures. These BST thin film band-pass filters have been designed by the 2.5 D field simulator, IE3D, Zeland Inc., and fabricated by thin film process. The simulation results, using the 2-pole microstrip, CPW, and CBCPW band-pass filters, show the center frequencies of 5.89 GHz, 5.88 GHz, and 5.69 GHz, and the corresponding insertion losses are 2.67 dB, 1.14 dB, and 1.60 dB, with 3 %, 9 %, and 7 % bandwidth, respectively. The measurement results show the center frequencies of 6.4 GHz, 6.14 GHz, and 6.04 GHz, and their corresponding insertion losses are 6 dB, 4.41 dB, and 5.41 dB, respectively, without any bias voltage. With the bias voltage of 40 V, the center frequencies for the band-pass filters are measured to be 6.61 GHz, 6.31 GHz, and 6.21 GHz, and their insertion losses are observed to be 7.33 dB, 5.83 dB, and 6.83 dB, respectively. From the experiment, the tuning range for the band-pass filters are determined as about 3 % ~ 8 %.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.131-136
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• 2008

Two Ka-band 3-stage power amplifiers were designed and fabricated using $0.18-{\mu}m$ CMOS technology. For low loss matching networks for the amplifiers, two substrate-shielded transmission line structures, having good modeling accuracy up to 40 GHz were used. The measured insertion loss of substrate-shielded microstrip-line (MSL) was 0.5 dB/mm at 27 GHz. A 3-stage CMOS amplifier using substrate-shielded MSL achieved a 14.7-dB small-signal gain and a 14.5-dBm output power at 27 GHz in a compact chip area of 0.83$mm^2$. The measured insertion loss of substrate-shielded coplanar waveguide (CPW) was 1.0 dB/mm at 27 GHz. A 3-stage amplifier using substrate-shielded CPW achieved a 12-dB small-signal gai and a 12.5-dBm output power at 26.5 GHz. This results shows a potential of CMOS technology for low cost short-range wireless communication components and system.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.15-23
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• 2007

This paper describes a dual frequency synthesizer designed in a 0.2$\mu$m CMOS technology for wireless LAN applications. The design is focused mainly on low-power characteristics. Power dissipation is minimized especially in VCO and prescaler design. The designed synthesizer includes all building blocks for elimination of external components, other than the crystal. Its operating frequency can be programmed by external data. It operates in the frequency range of 2.3GHz to 2.7GHz (RF) and 250MHz to 800MHz (IF) and consumes 5.14mA at 2.5GHz and 1.08mA at 0.5GHz from a 2.5V supply. The measured phase noise is -85dBc/Hz in-band and -105dBc/Hz at 1MHz offset at IF band. The die area is 1.7mm$\times$1.7mm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.281-286
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• 2007

In this paper, sub-circuits for 24 GHz phase locked 100ps(PLLs) using $0.5{\mu}m$ SiGe HBT are presented. They are 24 Ghz voltage controlled oscillator(VCO), 24 GHz to 12 GHz regenerative frequency divider(RFD) and 12 GHz to 1.5 GHz static frequency divider. $0.5{\mu}m$ SiGe HBT technology, which offers transistors with 90 GHz fMAX and 3 aluminum metal layers, is employed. The 24 GHz VCO employed series feedback topology for high frequency operation and showed -1.8 to -3.8 dBm output power within tuning range from 23.2 GHz to 26 GHz. The 24 GHz to 12 GHz RFD, based on Gilbert cell mixer, showed 1.2 GHz bandwidth around 24 GHz under 2 dBm input and consumes 44 mA from 3 V power supply including I/O buffers for measurement. ECL based static divider operated up to 12.5 GHz while generating divide by 8 output frequency. The static divider drains 22 mA from 3 V power supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3A
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• pp.179-184
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• 2003

In this paper, an asymmetric topology of MMIC SPDT switch was proposed to increase the isolation in the receiving path and decrease the insertion loss with higher P1dB in the transmitting path for the ISM band. This SPDT switch was implemented with 0.5㎛ GaAs MESFETs processed by ETRI for the IDEC MPW project. For the receiving path the measured insertion losses were 1.518dB at 3GHz and 1.777dB at 5.75GHz and the isolations were 38.474dB at 3GHz and 29.125dB at 5.75GHz. For the transmitting path the insertion losses were 0.916dB at 3GHz and 1.162dB at 5.75GHz and the isolations were 23.259dB at 3GHz and 16.632dB at 5.75GHz. Compared to the symmetric topology the isolations of the receiving path for the asymmetric one were improved by 15.9dB at 3GHz and 11.9dB at 5.75GHz and its insertion loss was increased by about 0.6dB. In addition, P1dB of 21.5 dBm for the transmitting path was obtained, which is increased by 3.86dB compared to the symmetric one.