• 한국추진공학회:학술대회논문집
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• 한국추진공학회 2005년도 제24회 춘계학술대회논문집
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• pp.343-346
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• 2005

전산 해석과 병렬처리를 이용하여 정사각 관 내부를 전파하는 데토네이션파의 삼차원 구조를 살펴보았다. 가변 비열비 공식과 간략화 된 일단계 Arrhenius 반응 모델과 연계된 비점성 유체 방정식을 MUSCL 기반 TVD 해법과 4단계 Runge-Kutta 적분 방법을 이용하여 해석하였다. 삼차원에서의 비정상 해석 결과로부터 그을음 막 기록(smoked-foil record)에서 같은 길이와 다른 폭을 가지는 수평 및 대각 방향 불안정에 의한 상세한 파면 구조를 파악할 수 있었다.

• 한국자동차공학회논문집
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• 제3권3호
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• pp.97-108
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• 1995

A 3-dimensional double track vehicle model, that has 12-degress-of-freedom, was proposed to analyze handling and riding behaviours of an automotive car. Nonlinear characteristics of the suspension and steering systems of the vehicle model were considered in its equations of motion, which were solved by using the 4th-order Runge-Kutta integration method. Computer simulations for lane change, steady-state handling, and running-over-bump manoeuvres were made and verified by vehicle tests on proving ground. The computed results of the proposed model showed better agreement with test results than those of the conventional 2-dimensional single track model did. Especially they showed good accuracy near the characteristic speed and in high lateral accelerated manoeuvres.

• Journal of Information Processing Systems
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• 제5권4호
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• pp.197-206
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• 2009

We introduce a novel high-level security metrics objective taxonomization model for software- intensive systems. The model systematizes and organizes security metrics development activities. It focuses on the security level and security performance of technical systems while taking into account the alignment of metrics objectives with different business and other management goals. The model emphasizes the roles of security-enforcing mechanisms, the overall security quality of the system under investigation, and secure system lifecycle, project and business management. Security correctness, effectiveness and efficiency are seen as the fundamental measurement objectives, determining the directions for more detailed security metrics development. Integration of the proposed model with riskdriven security metrics development approaches is also discussed.

• 한국세라믹학회지
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• 제41권4호
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• pp.273-276
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• 2004

Report ferroelectric memories based on 0.35$\mu\textrm{m}$ CMOS technology ensuring ten-year retention and imprint at 175$^{\circ}C$. This excellent reliability resulted from newly developed BT-based ferroelectric films with superior reliability performance at high temperatures, and also resulted from robust integration schemes free from ferroelectric degradation due to process impurities such as moisture and hydrogen. The superior reliabilities at high temperature of ferroelectric memories using BT-based films are due to the random orientation by special bake treatments.

• ETRI Journal
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• 제25권4호
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• pp.270-273
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• 2003

This paper presents a simple process to integrate thin-film inductors with a bottom NiFe magnetic core. NiFe thin films with a thickness of 2 to 3${\mu}m$ were deposited by sputtering. A polyimide buffer layer and shadow mask were used to relax the stress of the NiFe films. The fabricated double spiral thin-film inductor showed an inductance of 0.49${\mu}H$ and a Q factor of 4.8 at 8 MHz. The DC-DC converter with the monolithically integrated thin-film inductor showed comparable performances to those with sandwiched magnetic layers. We simplified the integration process by eliminating the planarization process for the top magnetic core. The efficiency of the DC-DC converter with the monolithic thin-film inductor was 72% when the input voltage and output voltage were 3.5 V and 6 V, respectively, at an operating frequency of 8 MHz.

• Structural Engineering and Mechanics
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• 제27권4호
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• pp.457-475
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• 2007

Analysis of transverse stresses at layer interfaces in a composite laminate has always been a challenging task. Composite structures possess highly irregular material properties at layer interfaces, which cause high shear stresses. Classical Plate Theory and First Order Shear Deformation Theory (FSDT) use post computing to calculate transverse stresses. This paper presents Reissner Mixed Variational Theorem (RMVT) based finite element model to carry out layer-wise analysis of composite laminates. Selective integration scheme has been used. The formulation has been validated by solving numerical examples and comparing the results with those published in the literature.

• Structural Engineering and Mechanics
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• 제15권4호
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• pp.463-476
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• 2003

This paper deals with nonlinear asymmetric dynamic buckling of clamped laminated angle-ply composite spherical shells under suddenly applied pressure loads. The formulation is based on first-order shear deformation theory and Lagrange's equation of motion. The nonlinearity due to finite deformation of the shell considering von Karman's assumptions is included in the formulation. The buckling loads are obtained through dynamic response history using Newmark's numerical integration scheme coupled with a Newton-Raphson iteration technique. An axisymmetric curved shell element is used to investigate the dynamic characteristics of the spherical caps. The pressure value beyond which the maximum average displacement response shows significant growth rate in the time history of the shell structure is considered as critical dynamic load. Detailed numerical results are presented to highlight the influence of ply-angle, shell geometric parameter and asymmetric mode on the critical load of spherical caps.

• Journal of Power Electronics
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• 제14권4호
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• pp.796-805
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• 2014

A digital controller with a low-power approach for point-of-load synchronous buck converters is discussed and compared with its analog counterpart to confirm its feasibility for system integration. The tri-mode digital controller IC in $0.35{\mu}m$ CMOS process is presented to demonstrate solutions that include a PID, quarter PID, and robust RST compensators. These compensators address the steady-state, stand-by, and transient modes according to the system operating point. An idle-tone free condition for ${\Sigma}-{\Delta}$ DPWM reduces the inherent tone noise under DC-excitation. Compared with that of the traditional approach, this condition generates a quasi-pure modulation signal. Experimental results verify the closed-loop performances and confirm the power-saving mechanism of the proposed controller.

• Journal of Power Electronics
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• 제16권4호
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• pp.1306-1315
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• 2016

Modern power systems driven by high-power converters have become inevitable in view of the ever increasing demand for electric power. The total power loss can be reduced by limiting the switching losses in such power converters; increased power efficiency can thus be achieved. A reduced switching frequency that is less than a few hundreds of hertz is applied to power converters that produce output waveforms with high distortion. Selective harmonic elimination pulse width modulation (SHEPWM) is an optimized low switching frequency pulse width modulation method that is based on offline estimation. This method can pre-program the harmonic profile of the output waveform over a range of modulation indices to eliminate low-order harmonics. In this paper, a SHEPWM scheme for three-phase three-leg neutral point clamped inverter is proposed. Aside from eliminating the selected harmonics, the DC capacitor voltages at the DC bus are also balanced because of the symmetrical pulse pattern over a quarter cycle of the period. The technique utilized in the estimation of switching angles involves the firefly algorithm (FA). Compared with other techniques, FA is more robust and entails less computation time. Simulation in the MATLAB/SIMULINK environment and experimental verification in the very large scale integration platform with Spartan 6A DSP are performed to prove the validity of the proposed technique.

• Transactions on Electrical and Electronic Materials
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• 제15권3호
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• pp.139-143
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• 2014

In this paper, an integrated low-voltage control circuit is introduced for a charge pump DC-DC boost converter. By exploiting the advantage of the integration of the feedback control circuit within CMOS technology, the charge pump boost converter offers a low-current operation with small ripple voltage. The error amplifier, comparator, and oscillator in the control circuit are designed with the supply voltage of 3.3 V and the operating frequency of 1.6~5.5 MHz. The charge pump converter with the 4 or 8 pump stages is measured in simulation. The test in the $0.35{\mu}m$ CMOS process shows that the load current and ripple ratio are controlled under 1 mA and 2% respectively. The output-voltage is obtained from 4.8 ~ 8.5 V with the supply voltage of 3.3 V.