• 전력전자학회논문지
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• 제17권4호
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• pp.291-297
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• 2012

Recently, Switching devices become cheaper, depending on the multi-level inverters are considered as the power-conversion systems for high-power and power-quality demanding applications. The multi-level inverters can reduce the THD(Total Harmonic Distortion) as the output which is similar sinusoidal waveform by synthesizing several capacitor DC voltages. However it has some disadvantages such as increased number of components, complex PWM control method. Therefore, this paper is proposed the new multi-level inverter topology using an new H-bridge output stage with a bidirectional auxiliary switch. The proposed topology is the 4-level 3-phase PWM inverter with less switching part than conventional multi-level inverters and reactive power control possible. In order to understand the new multi-level inverter, topology analysis and switching patterns and modes according to the current loop are described in this paper. The proposed multi-level inverter topology is validated through PSIM simulation and the experimental results are provided from a prototype.

• 전력전자학회논문지
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• 제7권2호
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• pp.111-120
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• 2002

멀티레벨 인버터 시스템은 낮은 고조파 성분과 높은 전력이 요구되는 분야에 매우 효율적인 시스템이다. 멀티레벨 인버터 시스템의 경우에 스위치 소자의 손실은 기존의 방법으로는 해석 할 수 없다. 그 이유는 각 스위치 소자의 손실이 2-레벨과는 다르게 서로 같지 않기 때문이다. 본 논문에서는 멀티레벨 인버터 시스템에 대한 전도 손실과 스위칭 손실의 간단하고 정확한 방법을 제안하였다. 제안된 방법의 타당함은 3-레벨과 4-레벨 다이오드 클램프드 인버터 시스템에 대해 증명하였다.

• 전력전자학회논문지
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• 제20권4호
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• pp.337-343
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• 2015

The multi-level inverters are highly efficient for high-power and medium-voltage AC driving applications, such as high-speed railway systems and renewable energy resources, because such inverters generate lower total harmonic distortion (THD) and electromagnetic interface (EMI). Lower switching stress occurs on switching devices compared with conventional two-level inverters. Depending on the multi-level inverter topology, the required components and number of switching devices are different, influencing the overall efficiency. Comparative studies of multi-level inverters based on loss analysis and output characteristic are necessary to apply multi-level inverters in high-power AC conversion systems. This paper proposes a theoretical loss analysis method based on piecewise linearization of characteristic curves of power semiconductor devices as well as loss analysis and output performance comparison of five-level neutral-point clamped, flying capacitor inverters, and high-level cascaded H-bridge multi-level inverters.

• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1610-1620
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• 2015

A major problem in conventional multilevel inverter is that an increase in power semiconductor switches causes an increase in cost and switching losses of the inverter. The multicarrier strategy adopted for the multilevel inverters has become more popular due to reduced cost, lower harmonic distortion, and higher voltage capability than the conventional switching strategy applied to inverters. Various topologies and modulation strategies have been reported for utility and drive applications. Level shifted based pulse width modulation techniques are proposed to investigate the performance of the multilevel inverter. The proposed work focuses on reducing the utilized switches so that the cost and the switching losses of the inverter do not go up and the consistent efficiency could be achieved. This paper presents the detailed analysis of these topologies. The analysis is based on the number of switches, DC sources, output level, maximum voltage, and the efficiency. As an illustration, single phase cascaded multilevel inverter topologies are simulated using MATLAB/SIMULINK and the experimental results demonstrate the viability of these inverters.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.110-113
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• 2005

This paper proposes high speed SRM drive system for blower with a new 4-level inverter and precise excitation position generator. For the high speed blower, a proper 12/8 SRM is designed and analyzed. In order to get a fast build-up and demagnetization of excitation a current, now 4-level inverter system is proposed. The proposed 4-level inverter has additional charge capacitor, power switch and diode in the conventional asymmetric converter. The charged high voltage is supplied to the phase winding for fast current build-up, and demagnetization current is charged to additional capacitor of 4-level inverter. In addition, a precise excitation position generator can reduce turn-on and turn-off angle error according to sampling period of digital control system. The proposed high speed SRM drive system is verified by computer simulation.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제54권4호
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• pp.195-200
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• 2005

In this paper, we proposed the electric circuit using one common arm of H-Bridge Inverters to reduce the number of switching component in multi-level inverter combined with H-Bridge Inverters and Transformers. and furthermore we suggested the new multi-level PWM inverter using PWM level to reduce THD(Total Harmonic Distortion). and we used the switching method that can be same rate of usage at each transformer. Also, we tested the proposed prototype 9-level inverter to clarify the proposed electric circuit and reasonableness of control signal for the proposed multi-level PWM inverter.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 전력전자학술대회
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• pp.315-316
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• 2019

This paper proposes the operation scheme and control method for a four-level hybrid half-bridge flying-capacitor inverter (4L-HHBFCI). With in-phase disposition level-shifted modulation (IPD), the flying capacitor voltage ripple is less than 1% of the reference value, while the line-to-line voltage total harmonic distortion is 23.27% at unity modulation index. The performance and effectiveness of the proposed inverter operation have been verified by simulation results.

• 반도체디스플레이기술학회지
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• 제14권4호
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• pp.72-77
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• 2015

Three-level diode clamped multilevel inverter, generally known as neutral point clamped (NPC) inverter, has an inherent problem causing neutral point (NP) potential variation. Until now, the NP potential problem of variation has been investigated and lots of solutions have also been proposed. This paper presents a neutral point voltage control technology using the anti-windup PI controller and offset technology of PWM (Pulse Width Modulation) to control the variation of NPC 3-phase three-level inverter neutral point voltage. And the proposed algorithm is tested and verified using a PLL (Phase Locked Loop) in order to synchronize the phase voltage from the line voltage of grid. It significantly improves the voltage balancing under a solar fluctuation conditions of the inverter. Experimental results show the good performance and effectiveness of the proposed method.

• Journal of Electrical Engineering and Technology
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• 제10권2호
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• pp.574-585
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• 2015

This paper aims to improve the performance of conventional direct torque control (DTC) drives proposed by Takahashi by extending the idea for 5-level inverter. Hybrid cascaded H-bridge topology is used to achieve inverter voltage vector composed of 5-level of voltage. Although DTC is very popular for its simplicity but it suffers from some disadvantages like- high torque ripple and uncontrollable switching frequency. To compensate these shortcomings conventional DTC strategy is modified for five levels voltage source inverter (VSI). Multilevel hysteresis controller for both flux and torque is used. Optimal voltage vector selection from precise lookup table utilizing 12 sector, 9 torque level and 4 flux level is proposed to improve DTC performance. These voltage references are produced utilizing a hybrid cascaded H-bridge multilevel inverter, where inverter each phase can be realized using multiple dc source. Fuel cells, car batteries or ultra-capacitor are normally the choice of required dc source. Simulation results shows that the DTC drive performance is considerably improved in terms of lower torque and flux ripple and less THD. These have been experimentally evaluated and compared with the basic DTC developed by Takahashi.

• 한국정보통신학회논문지
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• 제5권4호
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• pp.746-755
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• 2001

본 논문은 플라잉 커패시터 3-레벨 인버터 및 컨버터를 위한 스너버 회로를 제안하였다. 제안한 스너버회로는 Undeland 스너버를 기본 스너버로 사용하여 구성한 것으로서, 2-레벨 인버터에서 사용되어온 Undeland 스너버의 장점을 그대로 지니고 있다. 3-레벨 인버터 및 컨버터를 위해 제안한 스너버 회로와 기존의 RCD/RLD 스너버를 비교하면 1)사용소자의 수가 감소하며, 2) 낮은 과전압에 의한 스위칭 소자의 전압 스트레스가 감소하며, 3) 스너버 회로에서의 전력손실이 감소하여 전체 시스템에서의 효율이 개선된다. 본 논문에서는 제안한 스너버를 3-레벨 플라잉 커패시터 인버터에 적용하여 스너버 특성을 컴퓨터 시뮬레이션으로 분석하였으며 실험을 통해 제안한 스너버의 효용성을 입증하였다. 제안한 플라잉 커패시터 3-레벨 인버터 및 컨버터를 위한 스너버 회로를 구성하는 방법은 멀티레벨 인버터 및 컨버터에도 그대로 적용 할 수 있다.