• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.7
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• pp.750-755
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• 2003

This paper proposes a new three-line balun. The equivalent circuit of the proposed three-line balun is presented, and impedance matrix［Z］of the equivalent circuit is derived from the relationship between the current and voltage at each port. The design equation for a given set of balun impedance at input and output ports is presented using［S］parameters, which is transferred fom impedance matrix,［Z］. To demonstrate the feasibility and validity of design equation, multi-layer ceramic(MLC) chip balun operated in the 2.4 GHz ISM band frequency is designed and fabricated by the use of the low temperature co-fired ceramic(LTCC) technology. By employing both the proposed new three-line balun equivalent circuit and multi-layer configuration provided by LTCC technology, the 2012 size MLC balun is realized. Measured results of the multi-layer LTCC three-line balun match well with the full-wave electromagnetic simulation results, and measured in band-phase and amplitude balances over a wide bandwidth are excellent. This proposed balun is very easily applicable to multi-layer structure using LTCC as shown in the paper, and also can be realized with microstrip lines on PCB. This distinctive performance is very favorable for wireless communication systems such as wireless LAN(Local Area Network) and Bluetooth applications.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.15-22
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• 2013

Low-Temperature-cofired ceramics (LTCC) antenna packages have been extensively researched and utilized in recent years due to its excellent electrical properties and ease of implementing dense package integration topologies. This paper introduces some of the key research and development activities using LTCC packaging solutions for 60 GHz antennas at Samsung Electronics [1]. The LTCC 60 GHz antenna element topology is presented and its measured results are illustrated. However, despite its excellent performance, the high cost issues incurred with LTCC at millimeter wave (mmWave) frequencies for antenna packages remains one of the key impediments to mass market commercialization of mmWave antennas. To address this matter, for the first time to the author's best knowledge this paper alleviates the high cost of mmWave antenna packaging by devising a novel, broadband antenna package that is wholly based on low-cost, high volume FR4 Printed Circuit Board (PCB). The electrical properties of the FR4 substrate are first characterized to examine its feasibility at 60 GHz. Afterwards a compact multi-layer antenna package which exhibits more than 9 GHz measured bandwidth ($S_{11}{\leq}-10$ dB) from 57~66 GHz is devised. The measured normalized far-field radiation patterns and radiation efficiency are also presented and discussed.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.4 s.33
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• pp.37-41
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• 2004

As mobile communication devices use wide bands for large data transmission, Low Temperature Co-fired Ceramic(LTCC) has been a candidate for module substrate, for it provides better electrical properties and enables various embedded passive devices compared to conventional PCB. The LTCC, however, has applied in limited area because of non-uniform shrinkage. Hybrid heating was developed to raise sample temperature uniformly in a short period of time This leads to unidirectional sintering which enables sample to be sintered layer by layer from the bottom, resulting in more stable shape of interconnection at the top surface of the sample than conventional electric furnace heating. When sintering properties of substrate and electrical/mechanical properties of interconnection were compared, hybrid heating showed possibility to be applicable to substrate miniaturization and interconnection densification superior to electric furnace heating.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.4
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• pp.716-722
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• 2017

In this paper, a fully printed NFC tag operating at 13.56 MHz was designed and fabricated using silver nano-paste and carbon ink. The proposed NFC tag has a printed coil with an inductance of $2.74{\mu}H$ on a PI film for application to an NFC tag IC with an internal capacitance of 50 pF. Screen printing technology used in this paper has advantages such as large area printing for mass production, low cost and eco-friendly process compared to conventional PCB manufacturing process. The proposed structure consists of a circular coil implemented as a single layer using silver nano-paste and carbon ink, a jumper pattern for chip mounting between the outer edge and the center of the coil, and an insulation pattern between the coil and the jumper pattern. In order to verify the performance of the proposed NFC tag, we performed the measurements of the printing line width, thickness, line resistance, adhesion and environmental reliability, and confirmed the suitability of the NFC tag based on the full-printed manufacturing method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.1
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• pp.179-183
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• 2019

The system stability must be ensured from the switching noise due to the power conversion efficiency and power conversion system miniaturization. Therefore, countermeasures to reduce switching noise during power conversion are essential. Thus, in the previous paper, we constructed the DC / DC Buck Converter circuit using MPQ4432 driver of MPS, and simulated the switching noise characteristics which occurs when the components are arranged differently in the 4 - layer PCB circuit structure with reference plane. In this paper, two different simulated circuits are fabricated and the characteristics of the conducted emission and the radiated emission are analyzed in the same way as the simulation. As a result, it was confirmed that the Conducted Emission characteristic was reduced by 2 ~ 9dB in the low frequency band and 6 ~ 7dB in the high frequency band depending on the configuration of the current return path. And the radiated emission characteristic is reduced by 9 dB. Conducted emission simulation results show that 6 ~ 7dB in the low frequency range and 2 ~ 9dB in the measurement result are somewhat different. In the high frequency band, it is confirmed that the experimental and simulation results are about 7dB. And Radiated Emission confirmed 12dB decrease in simulation, but confirmed decrease of 9dB in measurement result. It is confirmed that there is a slight difference in the amount of reduction, but the design of the power conversion circuit improves the noise characteristics according to the configuration of the current return path.

• Journal of the Korean Applied Science and Technology
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• v.32 no.3
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• pp.512-521
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• 2015

In this research, environmental friendly organic acid containing microetching system to improve adhesion strength between photoresist resin and Copper Clad Laminate(CCL) was developed without using strong oxidant $H_2O_2$. Etching rate and surface contamination on CCL were examined with various etching conditions with different etchants, organic acids and additives. to develope an optimum microetching condition. Etching solution with 0.04 M acetic acid showed the highest etching rate $0.4{\mu}m/min$. Etching solution with the higher concentration of APS showed the higher etching rate but surface contamination on CCL is very serious. In addition, stabilizer solution also played an important role to control the surface contamination. As a result of research, the etching solution containing 0.04 M of acetic acid, 0.1 M of APS with 4 g/L of stabilizer solution(ST-1) was best to improve adhesion between CCL and photoresist resin as well as showed the most clean and rough surface with the etching rate of $0.37{\mu}m/min$.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.3
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• pp.258-264
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• 2004

In this paper, MMIC double balanced star mixer for 40 ㎓ was implemented on GaAs substrate with backside vias. In the design of the MMIC mixer, the design of balun and diode was required. A novel balun structure using microstrip to CPS was presented. The 40 ㎓ balun was designed based on the design experience of the scale-down balun by 2 ㎓. The balun may be suitable for fabrication in MMIC process with backside via and can easily be applied for DBM(Double Balanced Mixer). A Schottky diode was designed and implemented using p-HEMT process considering the compatability with other high frequency MMIC's fabricated on p-HEMT base process. Finally, the double balanced star mixer was fabricated using the balun and the p=HEMP Schottky diode. The measured performance of mixer shows 30 ㏈ conversion loss at 18 ㏈m LO power. This insufficient performance is caused by the unwanted diode at AlGaAs junction in vertical structure of p-HEMT. If the p-HEMT's gate is recessed to AlGaAs layer, and so the diode is eliminated, the mixer's performances will be improved.

• Korean Journal of Metals and Materials
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• v.47 no.12
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• pp.842-851
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• 2009

The long-term reliability of Sn-0.3wt%Ag-0.7wt%Cu solder joints was evaluated and compared with Sn-3.0wt%Ag-0.5wt%Cu under thermal shock conditions. Test vehicles were prepared to use Sn-0.3Ag-0.7Cu and Sn-3.0Ag-0.5Cu solder alloys. To compare the shear strength of the solder joints, 0603, 1005, 1608, 2012, 3216 and 4232 multi-layer ceramic chip capacitors were used. A reflow soldering process was utilized in the preparation of the test vehicles involving a FR-4 material-based printed circuit board (PCB). To compare the shear strength degradation following the thermal shock cycles, a thermal shock test was conducted up to 2,000 cycles at temperatures ranging from $-40^{\circ}C$ to $85^{\circ}C$, with a dwell time of 30 min at each temperature. The shear strength of the solder joints of the chip capacitors was measured at every 500 cycles in each case. The intermetallic compounds (IMCs) of the solder joint interfaces werealso analyzed by scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDS). The results showed that the reliability of Sn-0.3Ag-0.7Cu solder joints was very close to that of Sn-3.0Ag-0.5Cu. Consequently, it was confirmed that Sn-0.3Ag-0.7Cu solder alloy with a low silver content can be replaced with Sn-3.0Ag-0.5Cu.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.62-62
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• 2008

As micro-system move toward higher speed and miniaturization, requirements for embedding the passive components into printed circuit boards (PCBs) grow consistently. They should be fabricated in smaller size with maintaining and even improving the overall performance. Miniaturization potential steps from the replacement of surface-mount components and the subsequent reduction of the required wiring-board real estate. Among the embedded passive components, capacitors are most widely studied because they are the major components in terms of size and number. Embedding of passive components such as capacitors into polymer-based PCB is becoming an important strategy for electronics miniaturization, device reliability, and manufacturing cost reduction Now days, the dielectric films deposited directly on the polymer substrate are also studied widely. The processing temperature below $200^{\circ}C$ is required for polymer substrates. For a low temperature deposition, bismuth-based pyrochlore materials are known as promising candidate for capacitor $B_2Mg_{2/3}Nb_{4/3}O_7$ ($B_2MN$) multi layers were deposited on Pt/$TiO_2/SiO_2$/Si substrates by radio frequency magnetron sputtering system at room temperature. The physical and structural properties of them are investigated by SEM, AFM, TEM, XPS. The dielectric properties of MIM structured capacitors were evaluated by impedance analyzer (Agilent HP4194A). The leakage current characteristics of MIM structured capacitor were measured by semiconductor parameter analysis (Agilent HP4145B). 200 nm-thick $B_2MN$ muti layer were deposited at room temperature had capacitance density about $1{\mu}F/cm^2$ at 100kHz, dissipation factor of < 1% and dielectric constant of > 100 at 100kHz.