• Journal of the Microelectronics and Packaging Society
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• v.28 no.4
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• pp.31-39
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• 2021

In this paper, warpage analysis that separates PCB for PoP (Package on Package) into unit and substrate using FEM (Finite Element Method), analysis of the effect of layer thickness on warpage, and SN (Signal-to-Noise) ratio by Taguchi method was carried. According to the analysis result, the contribution of the circuit layer on warpage was very high in the unit PCB, and the contribution of the outer layer was particularly high. On the other hand, the substrate PCB had a high influence of the circuit layer on warpage, but it was relatively low compared to the unit PCB, and the influence of the solder resist was rather increased. Therefore, considering the unit PCB and the substrate PCB at the same time, it is desirable to design the PCB for PoP layer-by-layer structure so that the outer and inner circuit layers are thick, the top solder resist is thin, and the thickness of the bottom solder resist is between 5 ㎛ and 25 ㎛.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.6 s.109
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• pp.529-537
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• 2006

Multi-layer PCBs are of ien used In compact microwave circuit design as density of PCB layout is increased. In this paper, the crosstalk between coupled lines connected with vias in a 4-layer PCB is investigated theoretically based on the circiuit-concept approach. Coupled lines connected with vias in a 4-layer PCB are divided into three sections, which are coupled microstrip lines and upper via section, center via section, and lower via and coupled microstrip lines section, respectively. Each section is represented by ABCD matrix. By cascading these three ABCD matrices crosstalk between coupled lines connected with vias in a 4-layer PCB is approximately calculated. The validity of this theoretical approach is verified by comparing the calculated results with the simulated ones using HFSS.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.59-66
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• 2018

In this paper, we analyzed the usefulness of single-structured printed circuit board (PCB) modeling by using numerical analysis to model the PCB structure applied to a package for semiconductor purposes and applying modeling assuming a single structure. PCBs with circuit layer of 3rd and 4th were used for analysis. In addition, measurements were made on actual products to obtain material characteristics of a single structure PCB. The analysis results showed that if the PCB was modeled in a single structure compared to a multi-layered structure, the warpage analysis results resulting from modeling the PCB structure would increase and there would be a significant difference. In addition, as the circuit layer of the PCB increased, the mechanical properties of the PCB, the elastic coefficient and inertia moment of the PCB increased, decreasing the package's warpage.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.77-82
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• 2012

In this paper, the research of IC embedded PCB process is carried out. For embedding chips into PCB, solder-balls on chips were etched out and ABF(Ajinomoto Build-ip Film), prepreg and Cu foil was laminated on that to fabricate 6 layer build-up board. The chip of which solder ball was removed was successfully interconnected with PCB by laser drilling and Cu plating. However, de-lamination phenomenon occurred between chip surface and ABF during reflow and thermal shock. To solve this problem, de-smear and plasma treatment was applied to PI(polyimide) passivation layer on chip surface to improve the surface roughness. The properties of chip surface(PI) was investigated in terms of AFM(Atomic Force Micrometer), SEM and XPS (X-ray Photoelectron Spectroscopy). As results, nano-size anchor was evenly formed on PI surface when plasma treatment was combined with de-smear(NaOH+KMnO4) process and it improved thermal shock reliability ($260^{\circ}C$-10sec solder floating).

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.47-56
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• 2015

In this paper, the Thermal behavior and reliability characteristics of carbon CCL (Copper Claded Layer), which can be used as the core of HDI (High Density Interconnection) PCB (Printed Circuit Board) are evaluated through experiments and numerical analysis using CAE (Computer Aided Engineering) software. For the characterization of the carbon CCL, it is compared with the conventional FR-4 core and Heavy Cu core. From research results, the deformation amount of the flexure strength of PCB is the highest with pitch grade carbon and thermal behavior of PCB is lowest as temperature increases. In addition, TC (Thermal Cycling), LLTS (Liquid-to-Liquid Thermal Shock) and Humidity tests have been applied in the PCB with carbon core and the reliability of PCB with carbon core is confirmed through reliability tests. Also, possibility of uneven surface of the via hole and wear of the drill bit due to the carbon fibers are analyzed. surface of the via hole is uniform, the surface of the drill bit is smooth. Therefore, it is proved that the carbon CCL has the drilling workability of the same level as conventional core material.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.2
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• pp.639-643
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• 2018

As electronic systems become smaller and more portable, the need for power conversion continues to increase. In addition, system stability must be ensured from switching noise due to power conversion efficiency and power conversion system miniaturization. Therefore, countermeasures to reduce switching noise during power conversion are essential. In this paper, a DC/DC buck converter circuit is constructed, and the characteristics of switching noise generated when changing the parts layout in a four-layer printed circuit board (PCB) structure with a reference plane are compared and analyzed. In addition, switching noise characteristics were compared and analyzed through simulations when the parts layout was different in a two-layer PCB structure from which the reference planes were removed. As a result, it was confirmed that the radiated emissions characteristic is reduced by 12dB and the conducted emissions characteristic decreased by 7dB to 8dB, according to the current return path in the four-layer PCB structure. Thus, it was confirmed that the noise characteristics can be improved according to the configuration of the current return path when the power conversion circuit is designed.

• Korean Journal of Materials Research
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• v.24 no.4
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• pp.186-193
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• 2014

A thin Cu seed layer for electroplating has been employed for decades in the miniaturization and integration of printed circuit board (PCB), however many problems are still caused by the thin Cu seed layer, e.g., open circuit faults in PCB, dimple defects, low conductivity, and etc. Here, we studied the effect of heat treatment of the thin Cu seed layer on the deposition rate of electroplated Cu. We investigated the heat-treatment effect on the crystallite size, morphology, electrical properties, and electrodeposition thickness by X-ray diffraction (XRD), atomic force microscope (AFM), four point probe (FPP), and scanning electron microscope (SEM) measurements, respectively. The results showed that post heat treatment of the thin Cu seed layer could improve surface roughness as well as electrical conductivity. Moreover, the deposition rate of electroplated Cu was improved about 148% by heat treatment of the Cu seed layer, indicating that the enhanced electrical conductivity and surface roughness accelerated the formation of Cu nuclei during electroplating. We also confirmed that the electrodeposition rate in the via filling process was also accelerated by heat-treating the Cu seed layer.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1272-1278
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• 2009

The cancellation method of P/G(power/ground) plane resonances which are generated between the power plane and the ground plane in a 4-layer PCB(Printed Circuit Boards) with a via-hole for the improvement of the RE(Radiated Emission) characteristic is presented. The validity of the proposed method was confirmed from simulation and measurement of performances of signal transmission characteristic, intensities of edge-radiation and radiated emission of PCB with a via-hole.

• Journal of IKEEE
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• v.25 no.4
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• pp.591-597
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• 2021

This paper proposes an EMC-aware PCB design method to reduce electromagnetic emission, where trace length and teturn path of critical signal are shortened by changing chip location and trace layout on the PCB, while additional filters or decoupling capacitors are not required. In the proposed method, signal velocity is calculated for various signals on the PCB. Critical signal with the fastest signal velocity is determined and its return path is shortened as much as possible by placing chip location and trace routing first. Return path of critical signal should be carefully designed not to have discontinuity. Power plane and ground plane should be carefully designed not to be divided, since these planes are the reference of return path. The proposed method was applied to automotive directional Bluetooth speaker which failed to pass CISPR 32 and CISPR 25 EMC tests. Its PCB was redesigned based on the proposed method and it easily passed the EMC tests. The proposed method is useful to EMC-sensitive electronic equipments.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.4
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• pp.77-82
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• 2022

During etching process of PCB, the electroplated copper line and seed layer copper have different etching rates and it caused the over etching of copper line as well as undercut of lines. In this research, the effects of etchants composition on copper etching characteristics were investigated. The optimum concentration of hydrogen peroxide and sulfuric acid of etchants were obtained using polarization and OCV (open circuit voltage) analysis for both rolled copper and electroplated copper. The inhibiting effects of different inhibitors were investigated using OCV and ZRA (zero resistance ammeter) analysis. The galvanic current between electroplated copper and seed layer copper were measured using ZRA method. Inhibitors for least galvanic current could be chosen based on galvanic coupling in ZRA analysis.