• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.614-614
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• 2013

The effect of graphene growth parameters on the number of graphene layers were systematically studied and growth mechanism on copper substrate was proposed. Parameters that could affect the thickness of graphene growth include the pressure in the system, gas flow rate, growth pressure, growth temperature, and cooling rate. We hypothesis that the partial pressure of both the carbon sources and hydrogen gas in the growth process, which is set by the total pressure and the mole fraction of the feedstock, could be the factor that controls the thickness of the graphene. A synthetic method to produce such large area graphene films with precise thickness from mono- to few-layer would be ideal for chemists and physicists to explore the promising electronic applications of these materials. Here, large-area uniform mono-, bi-, and few-layer graphene films were successfully synthesized on copper surface in selective growth windows, with a finely tuned total pressure and $CH_4$/$H_{2gas}$ ratio. Our findings may facilitate both the large-area synthesis of well-controlled graphene features and wide range of applications of graphene.

• Applied Science and Convergence Technology
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• v.24 no.4
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• pp.117-124
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• 2015

A direct growth method of graphene on insulating substrate without catalyst etching and transfer process was developed using Au/Ni/a-C catalyst system. During the growth process, behavior of the Au/Ni catalyst was investigated using EDX, XPS, SEM, and Raman spectroscopy. The Au/Ni catalyst layer was evaporated during growth process of graphene. The graphene film was composed mono-layer flakes. The transmittance of the graphene film was ~80.6%.

• Transactions on Electrical and Electronic Materials
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• v.11 no.4
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• pp.190-193
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• 2010

This report covers an effective fabrication method of graphene nanoribbon for top-gated field effect transistors (FETs) utilizing electron beam lithography with a bi-layer resists (XR-1541/poly methtyl methacrylate) process. To improve the variation of the gating properties of FETs, the residues of an e beam resist on the graphene channel are successfully taken off through the combination of reactive ion etching and a lift-off process for the XR-1541 bi-layer. In order to identify the presence of graphene structures, atomic force microscopy measurement and Raman spectrum analysis are performed. We believe that the lift-off process with bi-layer resists could be a good solution to increase gate dielectric properties toward the high quality of graphene FETs.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.129-129
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• 2016

Graphene, as a single layer of $sp^2$-bonded carbon atoms packed into a 2D honeycomb crystal lattice, has attracted much attention due to its outstanding properties. In order to synthesize high quality graphene, transition metals, such as nickel and copper, have been widely employed as catalysts, which needs transfer to desired substrates for various applications. However, the transfer steps are not only complicated but also inevitably induce defects, impurities, wrinkles, and cracks of graphene. Furthermore, the direct synthesis of graphene on dielectric surfaces has still been a premature field for practical applications. Therefore, cost effective and concise methods for transfer-free graphene are essentially required for commercialization. Here, we report a facile transfer-free graphene synthesis method through nickel and carbon co-deposited layer. In order to fabricate 100 nm thick NiC layer on the top of $SiO_2/Si$ substrates, DC reactive magnetron sputtering was performed at a gas pressure of 2 mTorr with various Ar : $CH_4$ gas flow ratio and the 200 W DC input power was applied to a Ni target at room temperature. Then, the sample was annealed under 200 sccm Ar flow and pressure of 1 Torr at $1000^{\circ}C$ for 4 min employing a rapid thermal annealing (RTA) equipment. During the RTA process, the carbon atoms diffused through the NiC layer and deposited on both sides of the NiC layer to form graphene upon cooling. The remained NiC layer was removed by using a 0.5 M $FeCl_3$ aqueous solution, and graphene was then directly obtained on $SiO_2/Si$ without any transfer process. In order to confirm the quality of resulted graphene layer, Raman spectroscopy was implemented. Raman mapping revealed that the resulted graphene was at high quality with low degree of $sp^3$-type structural defects. Additionally, sheet resistance and transmittance of the produced graphene were analyzed by a four-point probe method and UV-vis spectroscopy, respectively. This facile non-transfer process would consequently facilitate the future graphene research and industrial applications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.12
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• pp.1064-1071
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• 2015

In this paper, the electrical characteristics of interdigital capacitor with single-layer and multi-layer graphene were compared and analyzed in the microwave region. In equivalent circuit, a capacitor coupled with graphene showed the clear difference in electrical components such as resistance, inductance, and capacitance. In particular, for the capacitor with single-layer graphene, additional inductance and resistance occurred and the electrode resistance was also increased. Meanwhile, the self-resonance frequency of capacitor was shifted toward lower frequency region and its transmitted characteristic was considerably improved at frequency ranging from 0.4 to 4 GHz. The electrical characteristics of the capacitor with multi-layer graphene were somewhat different than the bare capacitor. In conclusion, we could confirm that single-layer graphene greatly influenced the electrical characteristics and performances of interdigital capacitor compared to multi-layer graphene.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.490-490
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• 2011

Graphene, hexagonal network of carbon atoms forming a one-atom thick planar sheet, has been emerged as a fascinating material for future nanoelectronics. Huge attention has been captured by its extraordinary electronic properties, such as bipolar conductance, half integer quantum Hall effect at room temperature, ballistic transport over ${\sim}0.4{\mu}m$ length and extremely high carrier mobility at room temperature. Several approaches have been developed to produce graphene, such as micromechanical cleavage of highly ordered pyrolytic graphite using adhesive tape, chemical reduction of exfoliated graphite oxide, epitaxial growth of graphene on SiC and single crystalline metal substrate, and chemical vapor deposition (CVD) synthesis. In particular, direct synthesis of graphene using metal catalytic substrate in CVD process provides a new way to large-scale production of graphene film for realization of graphene-based electronics. In this method, metal catalytic substrates including Ni and Cu have been used for CVD synthesis of graphene. There are two proposed mechanism of graphene synthesis: carbon diffusion and precipitation for graphene synthesized on Ni, and surface adsorption for graphene synthesized on Cu, namely, self-limiting growth mechanism, which can be divided by difference of carbon solubility of the metals. Here we present that large area, uniform, and layer controllable graphene synthesized on Cu catalytic substrate is achieved by acetylene-assisted CVD. The number of graphene layer can be simply controlled by adjusting acetylene injection time, verified by Raman spectroscopy. Structural features and full details of mechanism for the growth of layer controllable graphene on Cu were systematically explored by transmission electron microscopy, atomic force microscopy, and secondary ion mass spectroscopy.

• Journal of the Korean Applied Science and Technology
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• v.32 no.2
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• pp.232-239
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• 2015

In this paper, we study the dry transfer technology utilizing PDMS (Polydimethylsiloxane) stamp of a large single-layer graphene grown on Cu-foil as catalytic metal by using Chemical Vapor Deposition (CVD). By changing the surface property of the target substrate through $UV/O_3$ treatment, we can transfer the graphene on the target substrate while minimizing mechanical damages of graphene layer. Multi-layer (1~4 layers) graphene was stacked on $SiO_2/Si$ wafer successfully by repeating thetransfer method/process and then optical transmittance and sheet resistance of graphene layers have been measured as a quality assessment.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.433.1-433.1
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• 2014

The research of graphene, a monolayer of carbon atoms with honeycomb lattice structure, has explosively increased after appeared in 2004. As a result, its high transmittance, mobility, thermal conductivity, and outstanding mechanical and chemical stability have been proved. Especially, many researches were executed about the field of transparent electrode highlighting material of substituting the indium tin oxide (ITO). In addition, qualitative and quantitative improvements have been achieved due to many synthesis methods were discovered. Among them, mostly used method is chemical vapour deposition of graphene grown on copper or nickel. The transmittance, mobility, sheet resistance, and other many properties are completely changed according to these two types of synthesis method of graphene. In this research, considering the difference of characteristics as the synthesis method of graphene, what types of graphene should be used and how to use it were studied. The stacked graphene harvested on copper and multi-layer graphene harvested on nickel were compared and analyzed, as a result, the transmittance of 90% and the sheet resistance of $70{\Omega}{\square}$ was showed even though stacked graphene layers were 4 layers. The reason that could bring these results is lowered sheet resistance due to stacked monolayer graphenes. Moreover, light output power of the three stacked graphene spreading layer shows the highest value, but light-emitting diode with multi-layer graphene died out from 12mA due to also its high sheet resistance. Therefore, we need to clarify about what types of graphene and how to use the graphene in use.

• Journal of Powder Materials
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• v.27 no.4
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• pp.305-310
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• 2020

In this study, partially dry transfer is investigated to solve the problem of fully dry transfer. Partially dry transfer is a method in which multiple layers of graphene are dry-transferred over a wet-transferred graphene layer. At a wavelength of 550 nm, the transmittance of the partially dry-transferred graphene is seen to be about 3% higher for each layer than that of the fully dry-transferred graphene. Furthermore, the sheet resistance of the partially dry-transferred graphene is relatively lower than that of the fully dry-transferred graphene, with the minimum sheet resistance being 179 Ω/sq. In addition, the fully dry-transferred graphene is easily damaged during the solution process, so that the performance of the organic photovoltaics (OPV) does not occur. In contrast, the best efficiency achievable for OPV using the partially dry-transferred graphene is 2.37% for 4 layers.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.329-329
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• 2016

Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity.