• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.178-183
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• 2006

The proposed triple-band compact chip antenna using coupled meander line and stacked meander structure for mobile RFID/PCS/WiBro. The proposed antenna is designed to operate at 900, 1,800, and 2,350 MHz, and is realized by parasitic coupled and stacked a meander line. Meander lines are using extend length of effective current path more than monopole and contribute miniaturization. The coupled meander line controls the excitations of the mobile RFID and PCS, stacked meander line controls the excitation of the WiBro. The fabricated antenna size is $10.98{\times}22.3{\times}0.98\;mm$. The resonance frequencies are 905 MHz, 1.77 GHz and 2.32 GHz. The impedance bandwidths are 24 MHz, 140 MHz and 92 MHz. The maximum gains of antenna are 0.34 dBi, 2.58 dBi and 0.4 dBi at resonance frequencies.

• ETRI Journal
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• v.34 no.5
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• pp.706-712
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• 2012

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.187-190
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• 2000

We presents the construction of radio frequency pad area array package modules which operate at radio frequency of 224MHz, and proposes the structure of RF module packages to improve its electrical characteristics. The module of RF PAA package was constructed in the configuration of three dimensional stacked package and reduced size. RF PAA packages showed the optimized and improved gain of 2dB by partitioning the RF transceiver with 3 dimensional stacked PAA packages.

• Journal of the Korean institute of surface engineering
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• v.56 no.3
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• pp.180-184
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• 2023

Scholars have proposed wafer-level bonding and three-dimensional (3D) stacked integrated circuit (IC) and have investigated Cu-Cu bonding to overcome the limitation of Moore's law. However, information about quantitative Cu-Cu direct-bonding conditions, such as temperature, pressure, and interfacial adhesion energy, is scant. This study determines the optimal temperature and pressure for Cu-Cu bonding by varying the bonding temperature to 100, 150, 200, 250, and 350 ℃ and pressure to 2,303 and 3,087 N/cm². Various conditions and methods for surface treatment were performed to prevent oxidation of the surface of the sample and remove organic compounds in Cu direct bonding as variables of temperature and pressure. EDX experiments were conducted to confirm chemical information on the bonding characteristics between the substrate and Cu to confirm the bonding mechanism between the substrate and Cu. In addition, after the combination with the change of temperature and pressure variables, UTM measurement was performed to investigate the bond force between the substrate and Cu, and it was confirmed that the bond force increased proportionally as the temperature and pressure increased.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.3-17
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• 2003

.Package Trend -> Memory : Lighter, Thinner, Smaller & High Density => SiP, 3D Stack -> MPU : High Pin Counts & Multi-functional => FCBGA .Interposer Trend -> Via - Unfilled Via => Filled Via - Staggered Via => Stacked Via -> Emergence of All-layer Build-up Processes -> Interposer Material Requirement => Low CTE, Low $D_{k}$, Low $D_{f}$, Halogen-free .New Technology Concept -> Embedded Passives, Imprint, MLTS, BBUL etc.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.6
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• pp.919-930
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• 2001

This paper presents a wideband technique of impedance and axial-ratio bandwidth which uses the stacked planar array structure through optimum design of sub-polarization generating sections and parasitic patch. So, the effect of the dual-resonance characteristic can contribute to the bandwidth expansion of single fed planar array antenna using circular polarization which doesn\`t hire previous bandwidth expansion technique. The antenna can be used as a dual-band antenna by adjusting the resonance frequencies as well, and then the antenna is designed and fabricated in the frequency band of domestic satellite-TV service. This antenna has the performance of 9.7 % impedance bandwidth and 24 dBi of antenna gain. And it has also 2.8 % and 1.4 % of 3 dB Axial-ratio bandwidth at 11.4 GHz and 11.8 GHz respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1739-1741
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• 2007

A 3D projection display using stacked screens to display the near and far images, respectively, is developed. The front screen is made of a scattering polarizer film, and the far image on the rear screen is clearly visible through it. The image is perceived as three-dimensional, and no eyestrain is suffered.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.14 no.3
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• pp.31-37
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• 2015

In this paper, newly proposed dual-band microstrip antennas using stacked inverted-L-shaped parasitic elements are presented for GPS $L_1(1.575GHz)$ and $L_2(1.227GHz)$ bands. For making dual band which has large interval, ${\lambda}/4$($L_1$ band) inverted-L-shaped parasitic elements were stacked at both side of radiation apertures on the half-wavelength($L_2$ band) patch antennas. The resonance in the parasitic elements occurs through coupling to the patch. Next, due to using circular polarization at GPS, ${\lambda}/4$($L_1$ band) inverted-L-shaped parasitic elements was stacked using sequential rotation technique on the patch and both side of the diagonal corners of the antenna were eliminated to make dual-band circular polarization. The designed circular polarized antenna's dimensions are $0.43{\lambda}L{\times}0.43{\lambda}L{\times}0.06{\lambda}L$ (${\lambda}L$ is the free-space wavelength at 1.227 GHz). Measured -10 dB bandwidths was 120 MHz(7.6%) and 82.5 MHz(6.7%) at GPS $L_1$ and $L_2$ bands. and 3 dB axial ration bandwidths are 172 MHz(10.9%) and 25 MHz(2.03%), respectively. All of these cover the respective required system bandwidths. Within each of the designed bands, broadside radiation patterns were observed.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.381-382
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• 2012

• Journal of the Korea Society of Computer and Information
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• v.16 no.6
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• pp.1-10
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• 2011

In designing multi-core processors, interconnection delay is one of the major constraints in performance improvement. To solve this problem, the 3-dimensional integration technology has been adopted in designing multi-core processors. The 3D multi-core architecture can reduce the physical wire length by stacking cores vertically, leading to reduced interconnection delay and reduced power consumption. However, the power density of 3D multi-core architecture is increased significantly compared to the traditional 2D multi-core architecture, resulting in the increased temperature of the processor. In this paper, the floorplan methods which change the forms of vertical placement of the core and the level-2 cache are analyzed to solve the thermal problems in 3D multi-core processors. According to the experimental results, it is an effective way to reduce the temperature in the processor that the core and the level-2 cache are stacked adjacently. Compared to the floorplan where cores are stacked adjacently to each other, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% in the case of 4-layers, and by 13% in the case of 2-layers.