• Journal of the Korean Ceramic Society
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• v.41 no.3
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• pp.216-220
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• 2004

This paper is concerned with the development of stacked ceramic thin actuation layer IDEAL (InterDigitated Electrode Actuation Layer) using d$_{33}$ actuation mechanism of piezoelectric ceramic. Most of the thin piezoelectric actuators are operated with d$_{31}$ actuation mechanism. Many kinds of piezoelectric ceramic actuators are strived now to improve the actuation performance. One of efforts to improve performance of piezoceramic actuators is the research trying to develop an actuator using the piezoelectric coefficient d$_{33}$ . The piezoelectric coefficient d$_{33}$ is almost twice larger than piezoelectric coefficient d$_{31}$ . Therefore, the induced strain of PZT thin layer with d$_{33}$ 3 actuation mechanism is bigger than that with d$_{31}$ actuation mechanism. The AFC(MIT) and LaRC-MFC$^{TM}$ which is developed by a research team of NASA Langley Research Center used d$_{33}$ actuation mechanism with surface interdigitated electrode to enhance its actuation performance. But their actuation mechanism is not perfect d$_{33}$ actuation mechanism since the interdigitated electrodes are placed at the surface of the actuation layer. In this research, the stacked ceramic thin actuation layer with imbedded interdigitated electrode is designed and manufactured. The actuation strain of stacked ceramic thin actuation layer is measured and compared with the actuation strain of the LaRC-MFC$^{TM}$. The comparison shows that the developed stacked ceramic thin actuation layer can produce 15% more actuation strain than LaRC-MFC$^{TM}$.> TM/.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.118-119
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• 2007

High performance three-dimensional (3-D) stacked poly-Si complementary metal-oxide semiconductor (CMOS) inverters with a high quality laser crystallized channel were fabricated. Low temperature crystallization methods of a-Si film using the excimer-laser annealing (ELA) and sequential lateral solidification (SLS) were performed. The NMOS thin-film-transistor (TFT) at lower layer of CMOS was fabricated on oxidized bulk Si substrate, and the PMOS TFT at upper layer of CMOS was fabricated on interlayer dielectric film. The 3-D stacked poly-Si CMOS inverter showed excellent electrical characteristics and was enough for the vertical integrated CMOS applications.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.1
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• pp.7-13
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• 2013

3D stacked IC is one of the promising candidates which can keep Moore's law valid for next decades. IC can be stacked through various bonding technologies and they were reviewed in this report, for example, wafer direct bonding and atomic diffusion bonding, etc. As an effort to reduce the high temperature and pressure which were required for high bonding strength in conventional Cu-Cu thermo-compression bonding, surface activated bonding, solid liquid inter-diffusion and direct bonding interface technologies are actively being developed.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.225-230
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• 2005

The proposed Triple-band Compact Chip Antenna using Coupled Meander line and stacked meander Structure for Mobile RFID/PCS/WiBro. The proposed antenna is designed to operate at 900, 1800, and 2350 MHz, and is realized by parasitic coupled and stacked a meander line. Meander lines are using extend length of effective current path more than monopole and contribute miniaturization. The coupled meander line controls the excitations of the Mobile RFID and PCS, stacked meander line controls the excitation of the WiBro. The proposed antenna size is $11mm\times22.5mm\times1mm$. The antenna supports 900MHz, 1800MHz and 2350MHz operations simultaneously with bandwidths of 33MHz, 230MHz and 100MHz, respectively. The proposed antenna gains are result of simulation to be -0.8dBi, 3dBi and 3.8dBi, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.270-277
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• 2012

This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.2
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• pp.41-46
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• 2015

The demand on low power and high performance system is soaring due to the extending of mobile and small electronic device market. The 3D die-stacking technology is widely studying for next generation integration technology due to its high density and low access time. We proposed the 3D die-stacked DRAM including a reconfigurable accelerator in a logic layer of DRAM. Also we discuss and suggest a cache-based local memory for a reconfigurable accelerator in a logic layer. The reconfigurable accelerator in logic layer of 3D die-stacked DRAM reduces the overhead of data management and transfer due to the characteristics of its location, so that can increase the performance highly. The proposed system archives 24.8 speedup in maximum.

• Journal of IKEEE
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• v.28 no.2
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• pp.234-238
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• 2024

This paper presents a study on the integration of 3D-stacked dual-tip RRAM with a CNN accelerator architecture, leveraging its low drive current characteristics and scalability in a 3D stacked configuration. The dual-tip structure is utilized in a parallel connection format in a synaptic array to implement multi-level capabilities. It is configured within a Network-on-chip style accelerator along with various hardware blocks such as DAC, ADC, buffers, registers, and shift & add circuits, and simulations were performed for the CNN accelerator. The quantization of synaptic weights and activation functions was assumed to be 16-bit. Simulation results of CNN operations through a parallel pipeline for this accelerator architecture achieved an operational efficiency of approximately 370 GOPs/W, with accuracy degradation due to quantization kept within 3%.

• ETRI Journal
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• v.41 no.3
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• pp.396-407
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• 2019

Laser-assisted bonding (LAB) is an advanced technology in which a homogenized laser beam is selectively applied to a chip. Previous researches have demonstrated the feasibility of using a single-tier LAB process for 3D through-silicon via (TSV) integration with nonconductive paste (NCP), where each TSV die is bonded one at a time. A collective LAB process, where several TSV dies can be stacked simultaneously, is developed to improve the productivity while maintaining the reliability of the solder joints. A single-tier LAB process for 3D TSV integration with NCP is introduced for two different values of laser power, namely 100 W and 150 W. For the 100 W case, a maximum of three dies can be collectively stacked, whereas for the 150 W case, a total of six tiers can be simultaneously bonded. For the 100 W case, the intermetallic compound microstructure is a typical Cu-Sn phase system, whereas for the 150 W case, it is asymmetrical owing to a thermogradient across the solder joint. The collective LAB process can be realized through proper design of the bonding parameters such as laser power, time, and number of stacked dies.

• Progress in Superconductivity and Cryogenics
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• v.24 no.3
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• pp.47-51
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• 2022

With the innovative development of bio, pharmaceutical, and semiconductor technologies, it is essential to demand a next-generation transfer system that minimizes dust and vibrations generated during the manufacturing process. In order to develop dust-free and non-contact transfer systems, the high temperature superconductor (HTS) bulks have been applied as a magnet for levitation. However, sintered HTS bulk magnets are limited in their applications due to their relatively low critical current density (J_c) of several kA/cm² and low mechanical properties as a ceramic material. In addition, during cooling to cryogenic temperatures repeatedly, cracks and damage may occur by thermal shock. On the other hand, the bulk magnets made by stacked HTS tapes have various advantages, such as relatively high mechanical properties by alternate stacking of the metal and ceramic layer, high magnetic levitation performance by using coated conductors with high J_c of several MA/cm², consistent superconducting properties, miniaturization, light-weight, etc. In this study, we tried to fabricate HTS tapes stacked bulk magnets with 60 mm × 60 mm area and various numbers of HTS tape stacked layers for magnetic levitation. In order to examine the levitation forces of bulk magnets stacked with HTS tapes from 1 to 16 layers, specialized force measurement apparatus was made and adapted to measure the levitation force. By increasing the number of HTS tapes stacked layers, the levitation force of bulk magnet become larger. 16 HTS tapes stacked bulk magnets show promising levitation force of about 23.5 N, 6.538 kPa at 10 mm of levitated distance from NdFeB permanent magnet.

• Journal of Biomedical Engineering Research
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• v.31 no.4
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• pp.292-301
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• 2010

To restore visual sensation of blind patients, we have proposed a fully implantable retinal prosthesis comprising an three dimensionally (3D) stacked retinal chip for transforming optical signal to electrical signal, a flexible cable with stimulus electrode array for stimulating retina cells, and coupling coils for power transmission. The 3D stacked retinal chip is consisted of several LSI chips such as photodetector, signal processing circuit, and stimulus current generator. They are vertically stacked and electrically connected using 3D integration technology. Our retinal prosthesis has a small size and lightweight with high resolution, therefore it could increase the patients` quality of life (QOL). For realizing the fully implantable retinal prosthesis, we developed a retinal prosthesis module comprising a retinal prosthesis chip and a flexible cable with stimulus electrode array for generating optimal stimulus current. In this study, we used a 2D retinal chip as a prototype retinal prosthesis chip. We fabricated the polymide-based flexible cable of $20{\mu}m$ thickness where 16 channels Pt stimulus electrode array was formed in the cable. Pt electrode has an impedance of $9.9k{\Omega}$ at 400Hz frequency. The retinal prosthesis chip was mounted on the flexible cable by an epoxy and electrically connected by Au wire. The retinal prosthesis chip was cappted by a silicone to pretect from corrosive environments in an eyeball. Then, the fabricated retinal prosthesis module was implanted into an eyeball of a rabbit. We successfully recorded electrically evoked potential (EEP) elicited from the rabbit brain by the current stimulation supplied from the implanted retinal prosthesis module. EEP amplitude was increased linearly with illumination intensity and irradiation time of incident light. The retinal prosthesis chip was well functioned after implanting into the eyeball of the rabbit.