• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.8
• /
• pp.67-74
• /
• 2004

In this paper, a 3.3V 8-bit 500MSPS based on an interpolation architecture CMOS A/D converter is designed. In order to overcome the problems of high speed operation, a novel pre-amplifier, a circuit for the Reference Fluctuation, and an Averaging Resistor are proposed. The proposed Interpolation A/D Converter consists of Track ＆ Hold, four resistive ladders with 256 taps, 128 comparators, and digital blocks. The proposed A/D Converter is based on 0.35um 2-poly 4-metal N-well CMOS technology. The A/D Converter dissipates 440 mW at a 3.3 Volt single power supply and occupies a chip area of 2250um x 3080um.

• Journal of the Korean Society for Precision Engineering
• /
• v.16 no.9
• /
• pp.172-178
• /
• 1999

3D linear and circular interpolations are a basic part for the machining of complex shapes. Until now, because of the absence of appropriate algorithms for the generation of 3D lines and circles, a full accomplishment for available machine tool resolution is difficult. this paper presents new algorithms for 3D linear and circular interpolation in the reference pulse technique. In 3D space, the line or circle is not expressed as an implicit function, it is only defined as the intersection of two surfaces. A 3D line is defined as the intersection of two planes, and a 3D circle is defined as the intersection of a plane and the surface of a sphere. Based on these concepts, interpolation algorithms are designed to follow intersection curves in 3D space, and a real-time 3D linear and circular interpolator was developed in software using a PC. The algorithm implemented in a PC showed promising results in interpolation error and speed performance. It is expected that it can be applied to the next generation computerized numerical control systems for the machining of 3D lines, circles and some other complex shapes.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.41 no.12
• /
• pp.1748-1751
• /
• 2016

In this correspondence, we studied 3D uniform rectangular array as an extension of interpolation technique to compensate the beam pattern of 3D conformal array. The simulation result shows outstanding performance comparing to 2D interpolations.

• The KIPS Transactions:PartB
• /
• v.10B no.3
• /
• pp.339-346
• /
• 2003

In this paper, we propose a new method in which interpolation images are created by using a small number of axiai T2-weighted images instead of using many sectional images for 3D visualization of brain MR images. For image Interpolation, an important part of this process, we first segment a region of interest (ROI) that we wish to apply 3D reconstruction and extract the boundaries of segmented ROIs and MBR information. After the image size of interpolation layer is determined according to the changing rate of MBR size between top slice and bottom slice of segmented ROI, we find the corresponding pixels in segmented ROI images. Then we calculate a pixel's intensity of interpolation image by assigning to each pixel intensity weights detected by cube interpolation method. Finally, 3D reconstruction is accomplished by exploiting feature points and 3D voxels in the created interpolation images.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.3
• /
• pp.18-27
• /
• 2010

In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage，due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.4
• /
• pp.14-23
• /
• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2017.04a
• /
• pp.106-108
• /
• 2017

본 논문에서는 휘어지거나 굴곡진 array인 3차원 conformal array의 beam pattern을 보정하고자 기존의 2차원에서 3차원으로 확장한 interpolation technique과 compressive sensing을 이용하여 3-D uniform rectangular array(3-D URA)에 적용하는 방법을 연구하였다. 시뮬레이션 결과는 compressive sensing이 interpolation technique보다 우수한 특성을 보여준다.

• Journal of IKEEE
• /
• v.17 no.3
• /
• pp.275-283
• /
• 2013

In this paper, a 8bit 10Ms/s CMOS Folding and Interpolation analog-to-digital convertor is proposed. The architecture of the proposed ADC is based on a Folding & Interpolation using FR(Folding Rate)=8, NFB(Number of Folding Block)=4, IR(Interpolation Rate)=8. The proposed ADC adopts a preamplifier sharing method to decrease the number of preamplifier by half comparing to the conventional ones. This chip has been fabricated with a 0.35[um] CMOS technology. The effective chip area is $1.8[mm]{\times}2.11[mm]$ and it consumes 20[mA] at 3.3 power supply with 10[MHz] clock. The INL is -0.57, +0.61 [LSB] and DNL is -0.4, +0.51 [LSB]. The SFDR is 48.9[dB] and SNDR is 47.9[dB](ENOB 7.6b) when the input frequency is 100[kHz] at 10[MHz] conversion rate.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.67 no.3
• /
• pp.391-397
• /
• 2018

This paper proposes a interpolation error compensation method for PMSM torque control. In PMSM torque control, two dimensions look-up table(2D-LUT) is used for current reference generation due to its stable and robust torque control performance. However, the stored data in 2D-LUT is discreet, it is impossible to store all over the operation range. To reduce the reference generation error in this region, the 2D-Interpolation method is conventionally used, however, this method still remains the error affected by the number of stored data. Besides, in the case stored by fixed unit, this error is increased in field weakening region because of the small number of stored data. In this paper, analyzing the cause of this interpolation error, and compensating the method to reduce this error. Proposed method is verified by the simulation and experiment.

• Journal of the Korean Society for Precision Engineering
• /
• v.19 no.5
• /
• pp.89-94
• /
• 2002

Increasing demands on precision machining using CNC machines have necessitated that the tool to move with a position error as small as possible in 3-dimensional (3D) space. This paper presents the simultaneous 3D machining with a retrofitted PC-NC milling machine. To achieve the simultaneous 3-axis motions, a new precision interpolation algorithm for 3D Non-Uniform Rational B-Spline(NURBS) curve is used. With this accurate and efficient algorithm for the generation of complex. 3D shapes, a real-time NURBS interpolator was developed using a PC and the simultaneous 3D machining is accomplished.