• Journal of the Korea Institute of Military Science and Technology
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• v.17 no.1
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• pp.90-95
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• 2014

The system design and the system performance analysis of 3D imaging laser radar system for the mapping purpose is addressed in this article. For the mapping, a push-bloom scanning method is utilized. The pulsed fiber laser with high pulse energy and high pulse repetition rate is used for the light source of laser radar system. The high sensitive linear mode InGaAs avalanche photo-diode is used for the laser receiver module. The time-of-flight of laser pulse from the laser to the receiver is calculated by using high speed FPGA based signal processing board. To reduce the walk error of laser pulse regardless of the intensity differences between pulses, the time of flight is measured from peak to peak of laser pulses. To get 3D image with a single pixel detector, Risley scanner which stirs the laser beam in an ellipsoidal pattern is used. The system laser energy budget characteristics is modeled using LADAR equation, from which the system performances such as the pulse detection probability, false alarm and etc. are analyzed and predicted. The test results of the system performances are acquired and compared with the predicted system performance. According to test results, all the system requirements are satisfied. The 3D image which was acquired by using the laser radar system is also presented in this article.

• ETRI Journal
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• v.37 no.4
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• pp.752-765
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• 2015

We propose a novel post-processing algorithm and its very-large-scale integration architecture that simultaneously uses the passive and active stereo vision information to improve the reliability of the three-dimensional disparity in a hybrid stereo vision system. The proposed architecture consists of four steps - left-right consistency checking, semi-2D hole filling, a tiny adaptive variance checking, and a 2D weighted median filter. The experimental results show that the error rate of the proposed algorithm (5.77%) is less than that of a raw disparity (10.12%) for a real-world camera image having a $1,280{\times}720$ resolution and maximum disparity of 256. Moreover, for the famous Middlebury stereo image sets, the proposed algorithm's error rate (8.30%) is also less than that of the raw disparity (13.7%). The proposed architecture is implemented on a single commercial field-programmable gate array using only 13.01% of slice resources, which achieves a rate of 60 fps for $1,280{\times}720$ stereo images with a disparity range of 256.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.682-685
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• 2002

In this paper, we defined necessary operations and functional blocks of a multiplexer for 3-D video systems and present our multiplexer design. We adopted the ITU-T's recommendation(H.222.0) to define the operations and functions of the multiplexer and explained the data structures and details of the design for multiview image processing. The data structure of TS(Transport Stream) and PES (Packetized Elementary Stream) in ITU-T Recommendation H.222.0 does not fit our multiview image processing system, because this recommendation is fur wide scope of transmission of non-telephone signals. Therefore, we modified these TS and PES stream structures. The TS is modified to DSS(3D System Stream) and PES is modified to SPDU(DSS Program Data Unit). We constructed the multiplexer through these modified DSS and SPDU. The number of multiview image channels is nine, and the image class employed is MPEG-2 SD(Standard Definition) level which requires a bandwidth of 2∼6 Mbps. The required clock speed should be faster than 54(= 6 ${\times}$ 9)㎒ which is the outer interface clock speed. The inside part of the multiplexer requires a clock speed of only 1/8 of 54㎒, since the inside part of the multiplexer operates by the unit of byte. we used ALTERA Quartus II and the FPGA verification for the simulation.

• Proceedings of the KSR Conference
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• 2008.11b
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• pp.1069-1077
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• 2008

The railway abrasion measurement system have to satisfy two conditions to increase the measurement accuracy as follows. The laser region which is projected on the rail have to be extracted without the geometrical distortion. The mapping of the acquired laser region data on the rail profile have to be processed exactly. But, the conventional railway abrasion measurement system is deeply effected by the foreign substance( dust, rainwater, and so on ) on the railway or the sensitive response characteristic of the laser to the external measurement circumstance, and then the measurement errors arise from above factors. When the laser region is projected on the rail extracts from the acquired image, the interference of the light with the same frequency as the laser system occurs the serious problems. In the process of the mapping between the railway profile and the extracted laser region, the measurement accuracy is very highly effected by the geometrical distortion and the abnormal variation. In this Paper, we propose the novel method to increase the accuracy of the railway abrasion measurement dramatically. we designed and manufactured the high precision and fast image processing board with DSP Core and FPGA to measure the railway abrasion. The image processing board has the capability that the image of 1024X1280 from camera can be processed with the speed of 480 frame/sec. And, we apply the image processing algorithm base on the wavelet to extract the laser region is projected on the rail exactly. Finally, we developed high precision railway abrasion measurement system with the error range less than +/-0.5mm by which 2D image data is covered 3D data and mapped on the rail profile using the camera model and the perspective transform.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.4
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• pp.381-388
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• 2015

In this paper, a wireless video streaming system is designed and implemented for TV white space applications. It consists of a RF transceiver module, a digital modem, a camera, and a LCD screen. A VGA resolution video is captured by a camera, modulated by modem, and transmitted by RF transceiver module, and finally displayed at a destination 2.6-inch LCD screen. The RF transceiver is based on direct-conversion architecture. Image leakage is improved by low pass filtering LO, which successfully covers the TVWS. Also, DC offset problem is solved by current steering techniques which control common mode level at DAC output node. The output power of the transmitter and the minimum sensitivity of the receiver is +10 dBm and -82 dBm, respectively. The channel bandwidth is tunable among 6, 7 and 8 MHz according to regulations and standards. Digital modem is realized in Kintex-7 FPGA. Data rate is 9 Mbps based on QPSK and 512ch OFDM. A VGA video is successfully streamed through the air by using the developed TV white-space RF communication module.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1263-1270
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• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.69-72
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• 2000

This paper shows the more improved design of MRI receiver compared to conventional one based on Elscint Spectrometer. At first, the low-cost ADC is 16 bits, 3MHz sampling A/D converter Comparing to conventional one with signal bits of 14 bits, this device with those of 16 bits helps getting Improved the image resolution improved. If frequency is designed centering around 7.6 MHz to be satisfied in 10 MHz of maximum input bandwidth of ADC. For 1st demodulation, fixed IF is used for the purpose of the implementing multi nuclei system. Control parts & partial digital parts are integrated on one chip(FPGA). In DDC(Digital Down Converter), we got required bandwidth of LPF by controlling its decimation rate. With above considerations, we designed optimal receiver for high resolution imaging to be implemented through PC interface & experimental test of receiver of MRI after receiver's fabrication.

• Proceedings of the KIEE Conference
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• 2002.06a
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• pp.67-71
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• 2002

In this paper, we propose a new deformable model based on non-linear elasticity, anisotropic behavior and the finite element method and developed the high-speed controller for haptic control. The proposed controller is based on the PCI/FPGA technology, which can calculate the real position and transmit the force data to device rapidly, The haptic system is composed of 6DOF force display device, high-speed controller and HIR library for 3D graphic deformation algorithm & haptic rendering algorithm. The developed system will be used on constructing the dynamical virtual environment. we demonstrate the relevance of this approach for the real-time simulating deformations of elastic objects. To show the efficiency of our system, we designed simulation program of force-reflecting, As the result of the experiment, we found that the controller has much higher resolution than some other controllers.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.102-113
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• 2014

This paper suggests a novel hardware architecture of a real-time rectification which is to remove vertical parallax of an image occurred in the pre-processing stage of stereo matching. As an off-line step, Matlab Toolbox which was designed by J.Y Bouguet, was used to calculate calibration parameter of the image. Then, based on the Heikkila and Silven's algorithm, rectification hardware was designed. At this point, to enhance the precision of the rectified image, floating-point unit was generated by using Xilinx Core Generator. And, we confirmed that proposed hardware design had higher precision compared to other designs while having the ability to do rectification in real-time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3A
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• pp.265-271
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• 2009

This paper proposes an efficient initial frequency estimator for Digital Video Broadcasting-Second Generation (DVB-S2). The initial frequency offset of the DVB-S2 is around ${\pm}5MHz$, which corresponds to 20% of the symbol rate at 25Msps. To estimate a large initial frequency offset, the algorithm which call provide a large estimation range is required. Through the analysis of the data-aided (DA) algorithms, we find that the Mengali and Moreli (M&M) algorithm can estimate a large initial frequency offset at low SNR. Since the existing frequency estimator based on M&M algorithm has a high hardware complexity, we propose the methods to reduce the hardware complexity of the initial frequency estimator. This can be achieved by reducing the number of autocorrelators and arctangents. The proposed architecture can reduce the hardware complexity about 64.5% compared to the existing frequency estimator and has been thoroughly verified on the Xilinx Virtex II FPGA board.