• Korean Journal of Materials Research
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• v.17 no.7
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.89-110
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• 2005

A new 3D integration technology using wafer-to-wafer and chip-to-wafer stacking method was described. It was demonstrated that 3D microprocessor, 3D shared memory, 3D image processing chip and 3D artificial retina chip fabricated using 3D integration technology were successfully operated. The possibility of applying 3D image processing chip and 3D artificial retina chip to Robot's eye was investigated. The possibility of implanting 3D artificial retina chip into human eye was investigated.

• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.3
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• pp.1-6
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• 2016

The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.

• Design & Manufacturing
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• v.12 no.3
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• pp.19-24
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• 2018

Fused deposition Modeling (FDM) is one of the most widely used for the prototype of parts at ease. The FDM 3D printing method is a lamination manufacturing method that the resin is melted at a high temperature and piled up one by one. Another term is also referred to as FFF (Fused Filament Fabrication). 3D printing technology is mainly used only in the area of prototype production, not in production of commercial products. Therefore, if FDM 3D printer is applied to the product process of commercial products when considered, the strength and dimensional accuracy of the manufactured product is expected to be important. In this study, the mechanical properties of parts made by 3D printing with FDM method were investigated. The aim of this work is to examine how the mechanical properties of the FDM parts, by changing of processing FDM printing direction and the height of stacking layer is affected. The effect of the lamination direction and the height of the stacking layer, which are set as variables in the lamination process, by using the tensile specimen and impact specimen after the FDM manufacturing process were investigated and analyzed. The PLA (Poly Lactic Acid) was used as the filament materials for the 3D printing.

• ETRI Journal
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• v.34 no.5
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• pp.706-712
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• 2012

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

• Journal of the Earthquake Engineering Society of Korea
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• v.27 no.6
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• pp.321-330
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• 2023

In this study, the structural performance of the specimen fabricated through 3D printing was evaluated through monotonic loading experiments analysis to apply to 3D printed structures. The compression and flexural experiments were carried out, and the experimental results were compared to the finite element model results. The loading directions of specimens were investigated to consider the capacity of specimens with different curing periods, such as 7 and 28 days. As a result, the strength tended to increase slightly depending on the stacking direction. Also, between the 3D-printed panel composite and the non-reinforced panel, the bending performance depended on the presence or absence of composite reinforcement.

• Korean Journal of Optics and Photonics
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• v.19 no.2
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• pp.140-143
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• 2008

The integrated external cavity laser has been fabricated with a 1550 nm FP-LD, an optical filter, a micro ball lens and accurate ceramic blocks using a micro-block stacking (MBS) technique. The integrated external cavity laser module whose size is only $2.0{\times}2.1{\times}0.7\;mm^3$ has been mounted on the TO-CAN package. For the case of the 1.8% transmission filter, the single mode characteristic has been obtained with the optical power of -27.1 dBm and the SMSR of 31.7 dB.

• Proceedings of the Materials Research Society of Korea Conference
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• 2007.05a
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• pp.15.1-15.1
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• 2007

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.67-88
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• 2005

Mold-Flow 3 Die Stack CSP of Mold array packaging with different Gate types. As high density package option such as 3 or 4 die stacking technologies are developed, the major concerning points of mold related qualities such as incomplete mold, exposed wires and wire sweeping issues are increased because of its narrow space between die top and mold surface and higher wiring density. Full 3D rheokinetic simulation of Mold flow for 3 die stacking structure case was done with the rheological parameters acquired from Slit-Die rheometer and DSC of commercial EMC. The center gate showed severe void but corner gate showed relatively better void performance. But in case of wire sweeping related, the center gate type showed less wire sweeping than corner gate types. From the simulation results, corner gate types showed increased velocity, shear stress and mold pressure near the gate and final filling zone. The experimental Case study and the Mold flow simulation showed good agreement on the mold void and wire sweeping related prediction. Full 3D simulation methodologies with proper rheokinetic material characterization by thermal and rheological instruments enable the prediction of micro-scale mold filling behavior in the multi die stacking and other complicated packaging structures for the future application.