• Journal of the Korea Society of Computer and Information
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• v.16 no.9
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• pp.1-10
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• 2011

Unfortunately, in current microprocessors, increasing the frequency causes increased power consumption and reduced reliability whereas it improves the performance. To overcome the power and thermal problems in the singlecore processors, multicore processors has been widely used. For 2D multicore processors, interconnection is regarded as one of the major constraints in performance and power efficiency. To reduce the performance degradation and the power consumption in 2D multicore processors, 3D integrated design technique has been studied by many researchers. Compared to 2D multicore processors, 3D multicore processors get the benefits of performance improvement and reduced power consumption by reducing the wire length significantly. However, 3D multicore processors have serious thermal problems due to high power density, resulting in reliability degradation. Detailed thermal analysis for multicore processors can be useful in designing thermal-aware processors. In this paper, we analyze the impact of workload distribution, distance to the heat sink, and number of stacked dies on the processor temperature. We also analyze the effects of the temperature on overall system performance. Especially, this paper presents the guideline for thermal-aware multicore processor design by analyzing the thermal problems in 2D multicore processors and 3D multicore processors.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.8
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• pp.1009-1023
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• 1999

이 논문은 재귀원형군 G(2^m , 2^k ) 그래프 이론적 관점에서 고찰하고 정점이 서로소인 경로에 관한 위상 특성을 제시한다. 재귀원형군은 1 에서 제안된 다중 컴퓨터의 연결망 구조이다. 재귀원형군 {{{{G(2^m , 2^k )의 서로 다른 두 노드 v와 w를 잇는 연결도 kappa(G)개의 서로소인 경로의 길이가 두 노드 사이의 거리d(v,w)나 혹은 G(2^m , 2^k )의 지름 \dia(G)에 비해서 얼마나 늘어나는지를 고려한다. 서로소인 경로를 재귀적으로 설계하는데, 그 길이는 k ge2일 때 d(v,w)+2^k-1과 \dia(G)+2^k-1의 최솟값 이하이고, k=1일 때 d(v,w)+3과 \dia(G)\+2의 최솟값 이하이다. 이 연구는 (2^m , 2^k )의 고장 감내 라우팅, 고장 지름이나 persistence의 분석에 이용할 수 있다.Abstract In this paper, we investigate recursive circulant G(2^m , 2^k ) from the graph theory point of view and present topological properties concerned with node-disjoint paths. Recursive circulant is an interconnection structure for multicomputer networks proposed in 1 . We consider the length increments of {{{{kappa(G)disjoint paths joining arbitrary two nodes v and win G(2^m , 2^k )compared with distance d(v,w)between the two nodes and diameter {{{{\dia(G)of G(2^m , 2^k ), where kappa(G)is the connectivity of G(2^m , 2^k ). We recursively construct disjoint paths of length less than or equal to the minimum of {{{{d(v,w)+2^k-1and \dia(G)+2^k-1for kge2 and the minimum of d(v,w)+3 and \dia(G)+2for k=1. This work can be applied to fault-tolerant routing and analysis of fault diameter and persistence of G(2^m , 2^k )

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.45-50
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• 2006

Copper via filling is the important factor in 3-D stacking interconnection of SiP (system in package). As the packaging density is getting higher, the size of via is getting smaller. When DC electroplating is applied, a defect-free hole cannot be obtained in a small size via hole. To prevent the defects in holes, pulse and pulse reverse current was applied in copper via filling. The holes, $20\and\;50{\mu}m$ in diameter and $100{\sim}190\;{\mu}m$ in height. The holes were prepared by DRIE method. Ta was sputtered for copper diffusion barrier followed by copper seed layer IMP sputtering. Via specimen were filled by DC, pulse and pulse-reverse current electroplating methods. The effects of additives and current types on copper deposits were investigated. Vertical and horizontal cross section of via were observed by SEM to find the defects in via. When pulse-reverse electroplating method was used, defect free via were successfully obtained.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.19-22
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• 2013

Recently, high speed transmission and large information demand have been increased. Also, researches of integrated optical device for large production and high-efficient planar lightwave circuit (PLC) have been increased. In this paper, integrated optical alignment is proposed which makes passive alignment between optical device and optical fiber possible. The integrated optical device consists of splitter structures which have one input and two outputs. The proposed integrated structure was fabricated by roll-to-roll (RTR) processing method. This method enables to manufacture continuously and the processing time can be shortened. Optical property of the fabricated optical device showed 3.9 dB insertion loss and 0.2 dB optical uniformity using the light source with 1550 nm wavelength.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2003.10a
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• pp.101-106
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• 2003

Recent electronic equipment becomes smaller, more functional, and more complex. According to these trends, LTCC(low temperature co-fired ceramic) has been emerged as a promising technology in packaging industry. It consists of multi-layer ceramic sheet, and the circuit has 3D structure. In this technology via hole formation plays an important role because it provides an electric path for the packaging interconnection network. Therefore via hole quality is very important for ensuring performance of LTCC product. Via holes are formed on the green sheet that consists of ceramic(before sintering) layer and PET(polyethylene Terephthalate) one. In this paper we found the correlation between hole quality and process condition such as ceramic thickness, and tool size. The shear behavior of double layer sheet by micro hole punching which is different from that of single layer one was also discussed.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.144-146
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• 2004

This paper presents experimental operation with utility invertactive 3kW photovoltaic generation system. And that describe configuration of utility interactive photovoltaic system which power supply for Demonstration experiment. The status of photovoltaic generation system comp-onents and interconnection and safety equipment will be summarized. This paper discusses property operation state which system endure division of power for demonstration experiment.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.12
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• pp.53-58
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• 1996

In this paper, a simple fabrication technique of an air-bridge for interconnection of isolated electrodes of microwave active and passive devices and MMIC's is proposed. The proposed air-bridge proceses are mainly combinations of thermal evaporation, positive photoresist and image reversal processes for easy lift-off of up to 2.0 .mu.m thick metal. According to the resutls of air-birdge processes, it is confirmed that air-gap and thickness of theair-bridge are about 3.5.mu.m, and 2.0.mu.m, respectively. And it is also possible to make the fine air-bridge with widths of 5~60.mu.m and post-intervals of 25~200.mu.m withot collapse. finally, GaAs power MESFET's and rectangular spiral inductors are fabricatd and measured in order to confirm of feasibility of the proposed air-bridge processes. The MAG of the fabricated power MESFET's is 10dB at 10GHz, and the inductance of the (200.mu. * 6 turns) rectangular spiral inductors 4.5 nH inX-band.

• Journal of the Microelectronics and Packaging Society
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• v.5 no.2
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• pp.21-26
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• 1998

대용량, 고속데이터 처리가 요구되는 System 개발은 이들의 복잡하고 고기능의 회 로 구현이 가능하냐에 달려 있고 또한 이들고기능 요구를 가장 잘 만족할수 있는 패키지는 MCM 이라 할 수있다. 시스템의 고속화, 소형화는 회로의 복잡성을 요구하는 있는 이를 패 키지로 구현하는 MCM은 시험성 확보에 심각한 문제점으로 나타나고 있다. 본 논문에서는 고밀도 구조의 MCM 기판에 대한 Interconnetion Line 시험검증을 위한 Flying Prober의 적 용 및 모듈 패키징 공정에 대한 조립성 검증을 위한 BST에 대해 설명한다. 연구에 사용된 MCM 모듈은 MCM-D 공정으로 제작되었으며 31um 신호선폭, 50um Via Hole Dia. 5신호 선층 5절연층 및 455 Net의 기판으로절연층은 Dow chemical의 BCB-4024/4026을 적용하였 다. 조립은 3 ASIC, 24소자 실장 및 2000 Wire Bonding으로 이루어지며 패키지는 방열특성 을 고려한 BGA(491 I /O,50mil pitch)를 개발하여 사용하였다. MCM 기판의미세패턴으로 구성된 Interconnection Line에 대해 Fine Ptich Probing이 가능한 Flying Prober를 사용하 여 평가하였으며 BST를 이용하여 실장소자의 KGD평가 및 능동, 수동소자가 실장된 MCM Package의 조립시험성을 확보할수 있었다.

• Transactions of Materials Processing
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• v.13 no.1
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• pp.65-71
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• 2004

Recent electronic equipment becomes smaller, more functional, and more complex. According to these trends, LTCC(low temperature co-fired ceramic) has been emerged as a promising technology in packaging industry. It consists of multi-layer ceramic sheet, and the circuit has 3D structure. In this technology via hole formation plays an important role because it provides an electric path for the packaging interconnection network. Therefore via hole qualify is very important for ensuring performance of LTCC product. Via holes are formed on the green sheet that consists of ceramic(before sintering) layer and PET(polyethylene terephthalate) one. In this paper we found the correlation between hole quality and process condition such as PET thickness and ceramic thickness. The shear behavior of double layer sheet by micro hole punching which is different from that of single layer one was also discussed.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.1
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• pp.35-42
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• 2003

Differential signaling has become a popular choice for high-speed interconnection schemes on Printed Circuit Boards (PCBs), offering superior immunity to external noise. However, conventional differential transmission lines on PCBs have problems, such as crosstalk and radiated emission. To overcome these, we propose a Twisted Differential Line (TDL) structure on a multi-layer PCB. Its improved immunity to crosstalk noise and the reduced radiated emission has been successfully demonstrated by measurement. The proposed structure is proven to transmit 3 Gbps digital signals with a clear eye-pattern. Furthermore, it is subject to much less crosstalk noise and achieves a 13 dB suppression of radiated emission. Index Terms - Twisted Differential Line, Differential Signaling, Crosstalk, Radiated Emission, Transmission Line, Twisted Pair