• Journal of the Korean Vacuum Society
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• v.5 no.3
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• pp.229-238
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• 1996

The electromigration phenomena and the characterizations of the conductor lifetime (Time-To-Failure, TTF) in Al-1%Si thin film interconnections under D.C. and Pulsed D.C. conditions were investigated . Meander type test patterns were fabricated with the dimensions of 21080$mu \textrm{m}$ length, 3$\mu\textrm{m}$ width, 0.7$\mu\textrm{m}$ thickness and the 0.1$\mu\textrm{m}$/0.8$\mu\textrm{m}$($SiO_2$/PSG)dielectric overlayer. The current densities of $2 \times10^6 A/\textrm{cm}^2$ and $1 \times10^7 A/\textrm{cm}^2$ were stressed in Al-1%Si thin film interconnection s under a D.C. condition. The peak current densities of $2 \times10^6 A/\textrm{cm}^2$ and $1 \times10^7 A/\textrm{cm}^2$ were also applied under a Pulsed D.C. condition at frequencies of 200KHz, 800KHz, 1MHz, and 4MHz with the duty factor of 0.5. THe time-to-failure under a Pulsed D.C.($TTF_{pulsed D.C}$) was appeared to be larger than that under a D.C. condition. It was found that the TTF under both a D.C. and a Pulsed D.C. condition. It was found that the TTF under both a D.C. and a Pulsed D.C. condition largely depends upon the appiled current densities respectively . This can be explained by a relaxation mechanism view due to a duty cycle under a Pulsed D.C. related to the wave on off. The relaxation phenomena during the pulsed off period result in the decayof excess vacancies generated in the Al-1%Si thin film interconnections because of the electrical and mechanical stress gradient . Hillocks and voids formed by an electromigration were observed by using a SEM (Scanning Electron Microscopy).

• Journal of Digital Contents Society
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• v.9 no.2
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• pp.203-211
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• 2008

Due to the advance of H/W and S/W techniques to play 3D sound, the virtual space contented by 3D graphics and sounds can provide users more improved realities and vividness. However for the small 3D contents developers and companies, it is hard to implement 3D sound techniques because the implementation requires expensive sound engines, 3D sound technical understanding and 3D sound programming skills. Therefore 3D-sound-playing-interface is necessary to easy and cost-effective 3D sound implementation. Using this interface, graphics experts can easily add 3D sound techniques to their applications. In this paper, the followings are designed and implemented as a preliminary stage in the way of developing the 3D sound playing interface. First, we develop 3D sound S/W modules converting mono to 3D sound in PC based systems. Second, we develop the interconnection modules to map 3D graphic objects and sound sources. The developed modules in this paper can allow the user to percept sound source position and surround effect at the moving positions in the virtual world. In the coming works, we are going to develop the more completed 3D sound playing interface consisted of the synchronization technique for sound and moving objects, and HRTF.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.295-301
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• 2008

Recently, the demand on mm-wave (millimeter-wave) applications has increased dramatically. While circuits operating in the mm-wave frequency band have been traditionally implemented in III-V or SiGe technologies, recent advances in Si MOSFET operation speed enabled mm-wave circuits realized in a Si CMOS technology. In this work, a 58 GHz CMOS LC cross-coupled VCO (Voltage Controlled Oscillator) was fabricated in a $0.13-{\mu}m$ Si RF CMOS technology. In the course of the circuit design, active device models were modified for improved accuracy in the mm-wave range and EM (electromagnetic) simulation was heavily employed for passive device performance predicttion and interconnection parasitic extraction. The measured operating frequency ranged from 56.5 to 58.5 GHz with a tuning voltage swept from 0 to 2.3 V. The minimum phase noise of -96 dBc/Hz at 5 MHz offset was achieved. The output power varied around -20 dBm over the measured tuning range. The circuit drew current (including buffer current) of 10 mA from 1.5 V supply voltage. The FOM (Figure-Of-Merit) was estimated to be -165.5 dBc/Hz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.112-117
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• 2008

Vertical interconnection scheme using novel silicon-through-via for 3D MEMS devices or stacked package is proposed and fabricated to demonstrate its feasibility. The suggested silicon-through-via replaces electroplated copper, which is used as an interconnecting material in conventional through-via, with doped silicon. Adoption of doped silicon instead of metal eliminates thermal-mismatch-induced stress, which can make troubles in high temperature MEMS processes, such as wafer bonding and LP-CVD(low pressure chemical vapor deposition). Two silicon layers of $30{\mu}m$ thickness are stacked on the substrate. The through-via arrays with spacing $40{\mu}m$ and $50{\mu}m$ are fabricated successfully. Electrical characteristics of the through-via are measured and analyzed. The measured resistance of the silicon-through-via is $169.9\Omega$.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.71-76
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• 2012

A chip interconnection technology for smart fabrics was investigated by using flip-chip bonding of SnBi low-temperature solder. A fabric substrate with a Cu leadframe could be successfully fabricated with transferring a Cu leadframe from a carrier film to a fabric by hot-pressing at $130^{\circ}C$. A chip specimen with SnBi solder bumps was formed by screen printing of SnBi solder paste and was connected to the Cu leadframe of the fabric substrate by flip-chip bonding at $180^{\circ}C$ for 60 sec. The average contact resistance of the SnBi flip-chip joint of the smart fabric was measured as $9m{\Omega}$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.4
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• pp.323-331
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• 1997

In this paper, the high efficiency balanced amplifier is presented as high efficiency power amplifier. This amplifier is basically composed of two FETs, an input power divider, output power combiner, input matching circuits, output matching circuits, second harmonic interconnection circuit and lowpass filter. The second harmonic interconnection circuit is composed of second harmonic frequency bandpass filter and transmission line. This circuit is inserted between the output terminals of the two FEF's output matching circuit, there is a second harmonic standing wave generated between two FET outputs. The electric wall termination is equivalent to the short circuit termination. As a result, the FET output termination condition needed to attain high efficiency is realized. Experimental high efficiency balanced amplifier is constructed to determine its practically attainable efficiency. The input VSWR is 1.27, and the output VSWR is 1.18. Power added efficiency of 75% is attained at 1.75 GHz band about 3W to balanced amplifier.

• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.336-338
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• 1996

In this paper, a simple control strategy to interconnect the utility line system for three-phase inverter. Conventionally, such interconnection is based on the 3-phase time-domain waveform analysis, though the control based on the plane defined by the two-axis theory is common in the area of the motor control. The new instantaneous power control strategy is introduced, which is based on the d-q axis theory. Simulation results show that proposed control method has good controllability with simple strategy.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.1117-1120
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• 2001

Chemical mechanical planarization(CMP) has emerged as the planarization technique of choice in both front-end and back-end integrated circuit manufacturing. Conventional CMP process utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. There have been serious problems in CMP in terms of repeatability and defects in patterned wafers. Since IBM's official announcement on Copper Dual Damascene(Cu2D) technology, the semiconductor world has been engaged in a Cu2D race. Today, even after~3years of extensive R&D work, the End-of-Line(EOL) yields are still too low to allow the transition of technology to manufacturing. One of the reasons behind this is the myriad of defects associated with Cu technology. Especially, dishing and erosion defects increase the resistance because they decrease the interconnection section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been interface hardness of the pad, optimization of the pattern structure as dummy patterns. Dishing & erosion are initially generated an uneven pressure distribution in the materials. These defects are accelerated by free abrasive and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. Minimizing the abrasive concentration by using Ce$O_2$ is the best solution for reducing dishing & erosion and for removal rate. This paper introduce dishing & erosion generating mechanism and a method for developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP.

• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.111-117
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• 2007

In this paper, a new marchand balun using broadside-coupled coplanar waveguide(CPW) on flexible printed circuit (FPC) is proposed. The proposed balun is designed based on the coupled line theory. The fabricated balun shows compact size and improved performance compared to the conventional microstrip line marchand balun. Measured amplitude and phase imbalance between the two balanced output ports are within 0.2 dB and $1^{\circ}$ respectively in a wide frequency range($1.63{\sim}3.44$ GHz). The proposed balun is expected to be used between various antennas and RF front-ends as a functional interconnection.