• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.1
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• pp.1-9
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• 1993

In recent days high perfermance graphic operation is needed, since computer graphics is widely used for computer-aided design and simulator using high resolution graphic card. In this paper a graphic accelerator is designd with the functions of graphic primitives generation and geometrical transformations. 1-D Systolic Array Processor for Matris Vector operation is designed and used in main ALU of a graphic accelerator, since these graphic algorithms have comonon operation of Matris Vector. Conclusively, in case that the resolution of graphic domain is 800$\times$600, and 33.3nsec operator is used in a graphic accelerator, 29732 lines per second and approximately 6244 circles per second is generated.

• Journal of Korea Game Society
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• v.4 no.3
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• pp.65-70
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• 2004

The conventional 3D graphic accelerator is mainly focused on high performance in the application area of computer graphic and 3D video game How ever the existing 3D architecture is not suitable for portable devices because of its huge power. So, we analyze the embedded 3D graphics renderer. After the analyzing, to reduce the power, triangle set-up stage and edge walking stage are executed sequentially while scan-line processing stage and span processing stage which control performance of 3D graphic accelerator are executed parallel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.857-864
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• 2006

This paper describes a design of low-power/small-area arithmetic circuits which are vector processing unit powering nit, divider unit and square-root unit for mobile 3D graphic accelerator. To achieve area-efficient and low-power implementation that is an essential consideration for mobile environment, the fixed-point f[mat of 16.16 is adopted instead of conventional floating-point format. The vector processing unit is designed using redundant binary(RB) arithmetic. As a result, it can operate 30% faster and obtained gate count reduction of 10%, compared to the conventional methods which consist of four multipliers and three adders. The powering nit, divider unit and square-root nit are based on logarithm number system. The binary-to-logarithm converter is designed using combinational logic based on six-region approximation method. So, the powering mit, divider unit and square-root unit reduce gate count when compared with lookup table implementation.

• Journal of Korea Multimedia Society
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• v.3 no.5
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• pp.526-534
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• 2000

There have been many researches on the 3D graphic accelerator for high speed by needs of CAD/CAM,3D modeling, virtual reality or medical image. In this paper, an SIMD processor architecture for 3D graphic accelerator is proposed in order to improve the processing time of the 3D graphics, and a parallel Phong shading algorithm is presented to estimate performance of the proposed architecture. The proposed SIMD processor architecture for 3D graphic accelerator consists of PCI local bus interface, 16 Processing Elements (PE's), and Park's multi-access memory system (NAMS) that has 17 memory modules. A serial algorithm for Phong shading is modified for the architecture and the main key is to divide a polygon into $4\times{4}$ squares. And, for processing a square, 4 PE's are regarded as a PE Grou logically. Since MAMS can support block access type with interval 1, it is possible that 4 PE Groups process a square at a time. In consequence, 16 pixels are processed simultaneously. The proposed SIMD processor architecture is simulated by CADENCE Verilog-XL that is a package for the hardware simulation. With the same simulated results as that of the serial algorithm, the speed enhancement by the parallel algorithm to the serial one is 5.68.

• Journal of IKEEE
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• v.15 no.3
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• pp.248-254
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• 2011

Recently, processing burden of CPU is growing because of graphical user interface according to enhance the performance of mobile devices and various graphical effects and creation of contents with 3D graphical effect or Flash animation. Therefore, the GPU are introduced to mobile device for support to variety contents. In this paper, OpenVG accelerator was implemented based on multi-core GP-GPU. OpenVG accelerator is verified using the sample image provided by Khronos group, and overall function is processed by only instruction set without dedicate hardware. The performance of processing the Tiger Image was 2 frames/sec.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.3-5
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• 2000

고성능의 3차원 그래픽 가속기 설계를 위해서는 어플리케이션, 하드웨어 구조, 수행모델 채택, 설계비용 등의 다양한 고려사항이 요구되고 따라서 각 모델에 따른 사전 시뮬레이션 환경구축은 반드시 필요하다. 이에 본 논문에서는 기본적인 3차원 그래픽 파이프라인 작업을 수행하여 다양한 결과를 보여주는 이식성 높은 시뮬레이션 환경을 제공함으로써 3차원 그래픽 가속하드웨어 세부모듈 설계에 필요한 설계 고려사항을 효과적으로 제시할 수 있게 하였다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.5
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• pp.97-103
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• 2010

There are many algorithms for 2D to 3D graphic conversion technology which have the high complexity and large scale of iterative computation. So in this paper propose parallel algorithm and high speed graphics accelerator architecture using Park's MAMS(Multiple Access Memory System) for Phong Shading, one of many 3D algorithms. The Proposed SIMD processor architecture is simulated by HDL and simulated and got 30 times faster result. It means any kinds of 3D algorithm can make parallel algorithm and accelerated by SIMD processor with Park's MAMS for real time processing.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.639-642
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• 2009

When the graphics accelerator for high-quality multimedia content design, hardware verification environment, easy and accurate performance evaluation in an embedded device is required. To work around this is not verified through the simulation waveform analysis to determine the actual calculated graphic images has designed a software rasterizer. Rasterizer is designed for Windows-based environment using the C language implementation of rasterization has a function at each step. Vertex data is entered and the results were verified.

• The Transactions of the Korea Information Processing Society
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• v.4 no.9
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• pp.2403-2411
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• 1997

Direct3D is a recently developed 3D graphic accelerator such that we could make a Windows graphic programs with Direct3D easily. This paper presents the fractal terrain model viewer developed in terms of Direct3D. The object classes and the input dialog box used the model viewer, program initializing process, and the flow of the model viewer are discussed. Finally, the output of terrain formulation in wire-frame, solid, and point type form are presented. To show the results, the data of a terrain model were made by a fractal technique, the midpoint displacement methods with square lattices of points.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.24-33
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• 2006

The effective geometry processing IP architecture for mobile SoC that has real time 3D graphics acceleration performance in mobile information system is proposed. Base on the proposed IP architecture, we design the floating point arithmetic unit needed in geometry process and the floating point geometry processor supporting the 3D graphic international standard OpenGL-ES. The geometry processor is implemented by 160k gate area in a Xilinx-Vertex FPGA and we measure the performance of geometry processor using the actual 3D graphic data at 80MHz frequency environment The experiment result shows 1.5M polygons/sec processing performance. The power consumption is measured to 83.6mW at Hynix 0.25um CMOS@50MHz.