• Title/Summary/Keyword: 3D Topology

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Character modeling using ZSphere (ZSphere를 활용한 캐릭터모델링)

  • Ryu, Chang-Su;Hur, Chang-Wu
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2011.10a
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    • pp.524-526
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    • 2011
  • ZSphere of ZBrush can be added to the screen, and most of all, added to the existing ZSphere as mobile geometrical objects. For example, legs can be produced out of the globoid in the progress of an intermediate step. characters with multiple limbs can be produced easily in this way. With Zsphere, several Child Spheres can be produced out of single Sphere, then these can be parents spheres, and can connect other Child Spheres. In this paper, by making each form through these processes, 3D characters were modeled to shape easily and rapidly. Since 3D objects can be added, rotated, and moved, they can interact smoothly with Z-depth of campus. To place these objects on the screen, paint, build fixed perspective image, smerge pixols and transform 3D objects, diverse transforming tools and sculpturing tools were used. The characters were designed in the way that first, the finished 3D characters were transformed into poly, then each side was restructured rapidly with Topology.

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Design of a Low Power Capacitor Cross-Coupled Common-Gate Low Noise Amplifier (캐패시터 크로스 커플링 방법을 이용한 5.2 GHz 대역에서의 저전력 저잡음 증폭기 설계)

  • Shim, Jae-Min;Jeong, Ji-Chai
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.3
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    • pp.361-366
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    • 2012
  • This paper proposes a low power capacitor cross-coupled 5.2 GHz band low noise amplifier(LNA) using the current-reused topology with the TSMC 0.18 ${\mu}m$ CMOS process. The proposed 5.2 GHz band LNA uses a capacitor cross-coupled $g_m$-boosting method for reducing current flow of circuit and a current-reused topology to decrease total power dissipation. The parallel LC networks are used to reduce size of spiral inductors. The simulation results show high gain of 17.4 dB and noise figure(NF) of 2.7 dB for 5.2 GHz.

THE OPTIMAL DESIGN OF CONNECTORS IN ALL CERAMIC FIXED PARTIAL DENTURES MANUFACTURED FROM ALUMINA TAPE (최적설계기법을 이용한 완전도재 가공의치의 연결부 형태 보강)

  • Oh Nam-Sik;Kim Han-Sung;Lee Myung-Hyun;Lee Keun-Woo
    • The Journal of Korean Academy of Prosthodontics
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    • v.42 no.2
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    • pp.125-132
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    • 2004
  • Statements of problem: All ceramic fixed partial denture cores can be made by the slip casting method and the advanced alumina tape method. The fracture resistance of these core connector areas is relatively low. Purpose: The purpose of this study is to standardize the appropriate volumetric figure and location of the connectors in the alumina core fabricated in alumina tape to be used in fixed partial dentures by way of topology optimization. Material and method: A maxillary anterior three-unit bridge alumina core with teeth form and surrounding periodontal apparatus model was used to ultimately design the most structurally rigid form of the connector. Loadings from a $0^{\circ}$, $45^{\circ}$ and $60^{\circ}$ to the axis of each tooth were applied and analyzed with the 3-D finite element analysis method. Using the results from these experiments, the topology optimization was applied and the optimal reinforcement layout of connector was obtained and the detail shape in the fixed partial denture core was designed. Results: The modified prosthesis with the form of a bulk in the lower lingual surface of the connector in the event, reduced the stress concentration up to 20% in the 3-D FEA. Conclusion: The formation of a bulk in the lower lingual connector area of an alumina core for a fixed partial denture decreases the stress to a clinically favorable measure but does not harm the esthetic point of view. This result illustrates the possibility of clinical application of the modified form designed by the topology optimization method.

Design of Spatial Relationship for 3D Geometry Model (3차원 기하모델에 대한 공간 관계 연산 설계)

  • Yi Dong-Heon;Hong Sung-Eon;Park Soo-Hong
    • Spatial Information Research
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    • v.13 no.2 s.33
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    • pp.119-128
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    • 2005
  • Most spatial data handled in GIS is two-dimensional. These two-dimensional data is established by selecting 2D aspects form 3D, or by projecting 3D onto 2D space. During this conversion, without user's intention, data are abstracted and omitted. This unwanted data loss causes disadvantages such as restrictingof the range of data application and describing inaccurate real world. Recently, three dimensional data is getting wide interests and demands. One of the examplesis Database Management System which can store and manage three dimensional spatial data. However, this DBMS does not support spatial query which is the essence of the database management system. So, various studies are needed in this field. This research designs spatial relationship that is defined in space database standard using the three-dimension space model. The spatial data model, which is used in this research, is the one defined in OGC for GMS3, and designing tool is DE-9IM based on Point-Set Topology blow as the best method for topological operation.

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Load and Capacitor Stacking Topologies for DC-DC Step Down Conversion

  • Mace, Jules;Noh, Gwangyol;Jeon, Yongjin;Ha, Jung-Ik
    • Journal of Power Electronics
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    • v.19 no.6
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    • pp.1449-1457
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    • 2019
  • This paper presents two voltage domain stacking topologies for powering integrated digital loads such as multiprocessors or 3D integrated circuits. Pairs of loads and capacitors are connected in series to form a stack of voltage domains. The voltage is balanced by switching the position of the capacitors in one case and the position of the loads in the other case. This method makes the voltage regulation robust to large differential load power consumption. The first configuration can be named the load stacking topology. The second configuration can be named the capacitor stacking topology. This paper aims at proposing and comparing these two topologies. Models of both topologies and a switching scheme are presented. The behavior, control scheme, losses and overall performance are analyzed and compared theoretically in simulation and experiments. Experimental results show that the capacitor stacking topology has better performance with a 30% voltage ripple reduction.

Design of MMIC SPDT Switches in the ISM Band Using GaAs MESFETs (GaAs MESFET를 이용한 ISM 대역 MMIC SPDT 스위치 설계)

  • Park, Hun;Yun, Kyung-Sik;Ji, Hong-Koo;Kim, Hae-Cheon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.3A
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    • pp.179-184
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    • 2003
  • In this paper, an asymmetric topology of MMIC SPDT switch was proposed to increase the isolation in the receiving path and decrease the insertion loss with higher P1dB in the transmitting path for the ISM band. This SPDT switch was implemented with 0.5㎛ GaAs MESFETs processed by ETRI for the IDEC MPW project. For the receiving path the measured insertion losses were 1.518dB at 3GHz and 1.777dB at 5.75GHz and the isolations were 38.474dB at 3GHz and 29.125dB at 5.75GHz. For the transmitting path the insertion losses were 0.916dB at 3GHz and 1.162dB at 5.75GHz and the isolations were 23.259dB at 3GHz and 16.632dB at 5.75GHz. Compared to the symmetric topology the isolations of the receiving path for the asymmetric one were improved by 15.9dB at 3GHz and 11.9dB at 5.75GHz and its insertion loss was increased by about 0.6dB. In addition, P1dB of 21.5 dBm for the transmitting path was obtained, which is increased by 3.86dB compared to the symmetric one.

Investigation to Metal 3D Printing Additive Manufacturing (AM) Process Simulation Technology (II) (금속 3D 프린팅 적층제조(AM) 공정 시뮬레이션 기술에 관한 고찰(II))

  • Kim, Yong Seok;Choi, Seong Woong;Yang, Soon Yong
    • Journal of Drive and Control
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    • v.16 no.3
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    • pp.51-58
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    • 2019
  • The objective of this study was to investigate a simulation technology for the AM field based on ANSYS Inc.. The introduction of metal 3D printing AM process, and the examining of the present status of AM process simulation software, and the AM process simulation processor were done in the previous study (part 1). This present study (part 2) examined the use of the AM process simulation processor, presented in Part 1, through direct execution of Topology Optimization, Ansys Workbench, Additive Print and Additive Science. Topology Optimization can optimize additive geometry to reduce mass while maintaining strength for AM products. This can reduce the amount of material required for additive and significantly reduce additive build time. Ansys Workbench and Additive Print simulate the build process in the AM process and optimize various process variables (printing parameters and supporter composition), which will enable the AM to predict the problems that may occur during the build process, and can also be used to predict and correct deformations in geometry. Additive Science can simulate the material to find the material characteristic before the AM process simulation or build-up. This can be done by combining specimen preparation, measurement, and simulation for material measurements to find the exact material characteristics. This study will enable the understanding of the general process of AM simulation more easily. Furthermore, it will be of great help to a reader who wants to experience and appreciate AM simulation for the first time.

An Ultra Wideband Low Noise Amplifier in 0.18 μm RF CMOS Technology

  • Jung Ji-Hak;Yun Tae-Yeoul;Choi Jae-Hoon
    • Journal of electromagnetic engineering and science
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    • v.5 no.3
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    • pp.112-116
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    • 2005
  • This paper presents a broadband two-stage low noise amplifier(LNA) operating from 3 to 10 GHz, designed with 0.18 ${\mu}m$ RF CMOS technology, The cascode feedback topology and broadband matching technique are used to achieve broadband performance and input/output matching characteristics. The proposed UWB LNA results in the low noise figure(NF) of 3.4 dB, input/output return loss($S_{11}/S_{22}$) of lower than -10 dB, and power gain of 14.5 dB with gain flatness of $\pm$1 -dB within the required bandwidth. The input-referred third-order intercept point($IIP_3$) and the input-referred 1-dB compression point($P_{ldB}$) are -7 dBm and -17 dBm, respectively.

Wavelet-Based Level-of-Detail Representation of 3D Objects (웨이브릿 기반의 3차원 물체 LOD 표현)

  • Lee, Ha-Sup;Yang, Hyun-Seung
    • Journal of KIISE:Computer Systems and Theory
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    • v.29 no.4
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    • pp.185-191
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    • 2002
  • In this paper, we propose a 3D object LOD(Level of Detail) modeling system that constructs a mesh from range images and generates the mesh of various LOD using the wavelet transform. In the initial mesh generation, we use the marching cube algorithm. We modify the original algorithm to apply it to construct the mesh from multiple range images efficiently. To get the base mesh we use the decimation algorithm which simplifies a mesh with preserving the topology Finally, when reconstructing new mesh which is similar to initial mesh we calculate the wavelet coefficients by using the wavelet transform. We solve the critical problem of wavelet-based methods - the surface crease problem (1) - by using the mesh simplification as the base mesh generation method.