• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.10
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• pp.41-48
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• 2008

This paper proposes a three-phase Z-source dynamic voltage restorer (Z-DVR) to mitigate the voltage sag for the critical loads. The proposed system is composed of passive filter and Z-source topology inverter. As an ESS(Energy Storage System) of the proposed system is employed the Proton Exchange Membrane Fuel Cells (PEMFC). To calculate and control the harmonics and compensation voltage, $i_{d}-i_{q}$ theory in dq rotating reference frame and PI controller are used. In case that three-phase voltage sags occurred, a PSIM simulation was done for the performance comparison of the conventional method employed battery stacks and proposed method. As a result, considering the voltage compensation performance, each method was nearly similar. Also, the compensation performance and the %THD(%Total Harmonic Distortion) result under the various source voltage conditions (sag or swell) were presented and discussed to show the performance of the proposed system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.1
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• pp.29-36
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• 2009

In this paper, the design and implementation of LNA and down-mixer using 90 nm CMOS process are presented for 60 GHz band WPAN receiver. In order to extract characteristics of the transistor used to design each elements under the optimum bias conditions, the S-parameter of the manufactured cascode topology was measured and the effect of the RF pad was removed. Measured results of 3-stages cascode type LNA the gain of 25 dB and noise figure of 7 dB. Balanced type down-mixer with a balun at LO input port shows the conversion gain of 12.5 dB within IF frequency($8.5{\sim}11.5\;GHz$) and input PldB of -7 dBm. The size and power consumption of LNA and down-mixer are $0.8{\times}0.6\;mm^2$, 43 mW and $0.85{\times}0.85\;mm^2$, 1.2 mW, respectively.

• Transactions on Electrical and Electronic Materials
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• v.17 no.2
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• pp.57-68
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• 2016

In this study, we present the modern hybrid system based power generation for electric vehicle applications. We describe the hybrid structure of modified current source based DC - DC converters used to extract the maximum power from Photovoltaic (PV) and Fuel Cell system. Due to reduced dc-link capacitor requirement and higher reliability, the current source inverters (CSI) better compared to the voltage source based inverter. The novel control strategy includes Distributed Maximum Power Point Tracking (DMPPT) for photovoltaic (PV) and fuel cell power generation system. The proposed DC - DC converters have been analyzed in both buck and boost mode of operation under duty cycle 0.5>d, 0.5<d<1 and 0.5<d for capable electric vehicle applications. The proposed topology benefits include one common DC-AC inverter that interposes the generated power to supply the charge for the sharing of load in a system of hybrid supply with photovoltaic panels and fuel cell PEM. An improved control of Direct Torque and Flux Control (DTFC) based induction motor fed by current source converters for electric vehicle.In order to achieve better performance in terms of speed, power and miles per gallon for the expert, to accepting high regenerative braking current as well as persistent high dynamics driving performance is required. A simulation model for the hybrid power generation system based electric vehicle has been developed by using MATLAB/Simulink. The Direct Torque and Flux Control (DTFC) is planned using Xilinx ISE software tool in addition to a Modelsim 6.3 software tool that is used for simulation purposes. The FPGA based pulse generation is used to control the induction motor for electric vehicle applications. FPGA has been implemented, in order to verify the minimal error between the simulation results of MATLAB/Simulink and experimental results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.673-684
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome this problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. Using the proposed gain control scheme, a low-voltage and high-speed CMOS VGA is designed. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than l.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$${\times}$360${\mu}{\textrm}{m}$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.8 s.111
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• pp.732-738
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• 2006

Divide-by-2 and divide-by-4 circuits which can operate up to 10 GHz are designed. A design method used in these circuits is the TSPC(True Single Phase Clocking) topology. The structure of the TSPC dividers is very simple because they need only a single clock and purely consist of smalt sized cmos devices. Through measurements, we find the fact that in proportion to the bias voltage, the free running frequency increases and the operation region also moves toward a higher frequency region. For operating conditions of bias voltage $3.0{\sim}4.0V$, input power 16dBm and dcoffset $1.5{\sim}2.0V$, 5 GHz and 2.5 GHz output signals divided by 2 and 4 are measured. The layout size of the divide-by-2 circuit is about $500{\times}500 um^2$($50{\times}40um^2$ except pad interconnection part).

• Journal of the Korea Institute of Military Science and Technology
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• v.23 no.3
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• pp.246-256
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• 2020

In the future Network Centric Warfare(NCW), changing to IPv6 based network environment is required to enable various future technologies such as the Internet of Things(IoT) and cloud technology which are expected to be introduced to the tactical network evolution. With the change to the IPv6 network, an ID/LOC(Identifier/Location) separation protocol that decomposes context of the IP address to location and identifier can enhance network capacity of increasing number of device and provide efficient mobility management in the tactical network that changes topology dynamically. In this paper, we choose ILNP(Identifier-Locator Network Protocol) as an ID/LOC separation for tactical network environment. In addition to ILNP-based tactical network design, this paper proposes a network-based mobility management scheme for providing efficient mobility management. Through numerical performance analysis, we show that the proposed scheme can reduce network loads more effectively than the conventional IP-based mobility management scheme and common handover procedure in ILNP.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.23 no.4
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• pp.375-384
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• 2005

Three dimensional urban models are being increasingly applied for various purposes such as city planning, telecommunication cell planning, traffic analysis, environmental monitoring and disaster management. In recent years, technologies from CAD and GIS are being merged to find optimal solutions in three dimensional modeling of urban buildings. These solutions include modeling of the interior building space as well as its exterior shape visualization. Research and development effort in this area has been performed by scientists and engineers from Computer Graphics, CAD and GIS. Computer Graphics and CAD focussed on precise and efficient visualization, where as GIS emphasized on topology and spatial analysis. Complementary research effort is required for an effective model to serve both visualization and spatial analysis purposes. This study presents an efficient way of using the CAD plans included in the building register documents to reconstruct the internal space of buildings. Topological information was built in the geospatial database and merged with the geometric information of CAD plans. as well as other attributal data from the building register. The GIS network modeling method introduced in this study is expected to enable an effective 3 dimensional spatial analysis of building interior which is developing with increasing complexity and size.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.62-68
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• 2010

This work proposes a 10b 100MS/s DAC based on a segmented local matching technique primarily for small chip area. The proposed DAC employing a segmented current-steering structure shows the required high linearity even with the small number of devices and demonstrates a fast settling behavior at resistive loads. The proposed segmented local matching technique reduces the number of current cells to be matched and the size of MOS transistors while a double-cascode topology of current cells achieves a high output impedance even with minimum sized devices. The prototype DAC implemented in a 0.13um CMOS technology occupies a die area of $0.13mm^2$ and drives a $50{\Omega}$ load resistor with a full-scale single output voltage of $1.0V_{p-p}$ at a 3.3V power supply. The measured DNL and INL are within 0.73LSB and 0.76LSB, respectively. The maximum measured SFDR is 58.6dB at a 100MS/s conversion rate.

• Journal of Power Electronics
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• v.18 no.2
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• pp.332-342
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• 2018

This paper proposes a parameter design method for multi-element resonant converters (MERCs) with a unique resonant zero point (RZP). This method is mainly composed of four steps. These steps include program filtration, loss comparison, 3D figure fine-tuning and priority compromise. It features easy implementation, effectiveness and universal applicability for almost all of the existing RZP-MERCs. Meanwhile, other design methods are always exclusive for a specific topology. In addition, a novel dual-CTL converter is also proposed here. It belongs to the RZP-MERC family and is designed in detail to explain the process of parameter selection. The performance of the proposed method is verified experimentally on a 500W prototype. The obtained results indicate that with the selected parameters, an extensive dc voltage gain is obtained. It also possesses over-current protection and minimal switching loss. The designed converter achieves high efficiencies among wide load ranges, and the peak efficiency reaches 96.9%.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.593-596
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• 2002

A design of clock and data recovery (CDR) circuit for the SONET OC-48 using a standard 0.18 ${\mu}m$ CMOS process has been performed. The phase detector and the charge pump must be able to operate at the 2.5 Gb/s input data speed and also accurately compare phase errors to reduce clock jitter. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output. A general ring oscillator topology is presented and simulated. It provides five-phase outputs and 220 MHz to 3.12 GHz tuning range.