• Title/Summary/Keyword: 3D Topology

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A Single-Pole, Eight-Throw, Radio-Frequency, MicroElectroMechanical Systems Switch for Multi-Band / Multi-Mode Front-End Module

  • Kang, Sung-Chan;Kim, Hyeon-Cheol;Chun, Kuk-Jin
    • Journal of Sensor Science and Technology
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    • v.20 no.2
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    • pp.77-81
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    • 2011
  • This paper presents a single-pole eight-throw(SP8T) switch based on proposed a radio-frequency(RF) microelectromechanical systems (MEMS) switches. The proposed switch was driven by a double stop(DS) comb drive, with a lateral resistive contact. Additionally, the proposed switch was designed to have tapered signal line and bi-directionally actuated. A forward actuation connects between signal lines and contact part, and the output becomes on-state. A reverse actuation connects between ground lines and contact part, and the output becomes off-state. The SP8T switch of 3-stage tree topology was developed based on an arrangement of the proposed RF MEMS switches. The developed SP8T switch had an actuation voltage of 12 V, an insertion loss of 1.3 dB, a return loss of 15.1 dB, and an isolation of 31.4 dB at 6 GHz.

Design methodology of the controller circuit for a highly efficient class D Amplifiers (D급 증폭기를 위한 제어회로의 설계)

  • Lee, Jong-Kue;Song, Pil-Jae
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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    • 2006.05a
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    • pp.407-409
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    • 2006
  • This paper presents the methods of designing the control circuits for a Class D amplifier to have a peak performance. The proposed approach is based on the three functional components - a carrier generator, a feedback circuit and a dead-time circuit. First the analog signal is applied to the controller, which outputs the 3 level PWM waveform. The controller used for this experiment is made of the operational amplifier and the logic circuit. The experimental results show that the control circuit performs with satisfaction and its output is proportional to input audio signal, providing a satisfactory 3 level PWM pattern. From this design methodology, by implementing a proposed control circuit we can achieve the efficient Class D amplifier using the half-bridge, full-bridge or push-pull topology at the output stage.

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Comparative Study on the Characteristics of Multilevel Inverter Topology (멀티레벨 인버터 토폴로지의 비교 연구)

  • Park, Jong-Je;Yun, Hong-Min;Na, Seung-Ho
    • Proceedings of the KIPE Conference
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    • 2012.07a
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    • pp.510-511
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    • 2012
  • 최근 전력변환 분야에서 고압 인버터의 요구가 증가함에 따라 국내외 Drive 업체에서 멀티레벨 인버터에 대한 관심이 커지고 있다. 특히, 현재 LS산전에서 양산되고 있는 Cascaded H-Bridge(이하 CHB) Type의 멀티레벨 인버터와 더불어 1981년 Nabae 교수에 의해 처음 제안된 3-Level Neutral Point Clamped(이하 NPC) Type의 멀티레벨 인버터는 최근 그 성능 및 신뢰성에 대한 검증이 많이 이루어 졌으며 경쟁사인 ABB/YASKAWA/TMEIC사(社) 등에서 실제 제품화가 되고 있다. 본 논문에서는 현재 LS산전에서 개발중인 3-Level NPC 인버터 기반의 5-Level NPC 인버터의 System 최적화를 위해 양산중인 CHB Type의 멀티레벨 인버터와 그 특성을 비교하여 해당 인버터 개발에 대한 타당성을 검증하였다.

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Syntax-based Accessibility Analysis Algorithm for Indoor Spaces (실내공간을 위한 기반 Syntax 접근성 분석 알고리즘)

  • Kim, Hye-Yeong;Jeon, Cheol-Min
    • Proceedings of the Korean Association of Geographic Inforamtion Studies Conference
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    • 2007.10a
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    • pp.247-256
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    • 2007
  • Accessibility is a field of study that has primarily been applied to urban or transportation problems two dimensionally. However, in large complex buildings as shopping centers or hospitals, inter-spatial accessibility among compartments has to be taken into account such as in building layouts or evacuation planning. This study expands space syntax theory, one of accessibility-related methodologies used for computing connectivity in urban or architectural spaces, into 3D indoor spaces. Although space syntax is basically a topology-based theory that does not consider general costs such as distance or time, this study suggests modification that incorporates different types of impedances in moving between places including distances, turns and transfers between floors. The proposed method is applied to a 3D campus building model in computing and displaying the accessibility to exit doors or cohesive accessibility among similar functions.

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Three Dimensional Topology of Vortical Structure of a Round Jet in Cross Flow (횡단류 제트 와류구조의 3차원 토폴로지)

  • Shin, Dae Sig;Kim, Kyung Chun
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.23 no.7
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    • pp.918-927
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    • 1999
  • In the fully developed internal flow fields, there are complex transition flows caused by interaction of the cross flow and jet when jet is Injected Into the flow. These interactions are studied by means of the flow visualization methods. An instantaneous laser tomographic method is used to reveal the physical mechanism and the structure of vortices formation in the branch pipe flow. The velocity range of cross flow of the pipe is 0.7m/s and the corresponding Reynolds number $R_{cf}$, based on the duct height is $5.6{\times}10^3$, diameter/height ratios(d/H) 0.14 and velocity ratios 3.0. Oil mist with the size of $10{\mu}m$ diameter is used for the scattering particle. The instantaneous topological features of the vortex ring roll-up of the jet shear layer and characteristics of this flow are studied in detail by performing flow visualization in rectangular duct flow. It is found that the formation and roll-up of ring vortices is a periodic phenomenon. The detailed topology of the vortices in the near field of a cross -flow jet and the mechanism associated with them give enforced hints of vortex breakdown within the vortex system due to the interaction of the jet and the cross-flow.

Totem-pole Bridgeless Boost PFC Converter Based on GaN FETs (GaN FET을 이용한 토템폴 구조의 브리지리스 부스트 PFC 컨버터)

  • Jang, Paul;Kang, Sang-Woo;Cho, Bo-Hyung;Kim, Jin-Han;Seo, Han-Sol;Park, Hyun-Soo
    • The Transactions of the Korean Institute of Power Electronics
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    • v.20 no.3
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    • pp.214-222
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    • 2015
  • The superiority of gallium nitride FET (GaN FET) over silicon MOSFET is examined in this paper. One of the outstanding features of GaN FET is low reverse-recovery charge, which enables continuous conduction mode operation of totem-pole bridgeless boost power factor correction (PFC) circuit. Among many bridgeless topologies, totem-pole bridgeless shows high efficiency and low conducted electromagnetic interference performance, with low cost and simple control scheme. The operation principle, control scheme, and circuit implementation of the proposed topology are provided. The converter is driven in two-module interleaved topology to operate at a power level of 5.5 kW, whereas phase-shedding control is adopted for light load efficiency improvement. Negative bias circuit is used in gate drivers to avoid the shoot-through induced by high speed switching. The superiority of GaN FET is verified by constructing a 5.5 kW prototype of two-module interleaved totem-pole bridgeless boost PFC converter. The experiment results show the highest efficiency of 98.7% at 1.6 kW load and an efficiency of 97.7% at the rated load.

A Design on UWB LNA for Using $0.18{\mu}m$ CMOS ($0.18{\mu}m$ CMOS공정을 이용한UWB LNA)

  • Hwang, In-Yong;Jung, Ha-Yong;Park, Chan-Hyeong
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.567-568
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    • 2008
  • In this paper, we proposed the design on LNA for $3{\sim}5\;GHz$ frequency with Using $0.18{\mu}m$CMOS technology. The LNA gain is 12-15 dB, and noise figure is lower than 5 dB and Input/output matching is lower than 10 dB in frequency range from 3 GHz to 5 GHz. The topology, which common source output of cascode is reduced noise figure and improved gain. Input common gate amplifier extend LNA's bandwidth.

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A 0.18-μm CMOS UWB LNA Combined with High-Pass-Filter

  • Kim, Jeong-Yeon;Kim, Chang-Wan
    • Journal of electromagnetic engineering and science
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    • v.9 no.1
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    • pp.7-11
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    • 2009
  • An Ultra-WideBand(UWB) Low-Noise Amplifier(LNA) is proposed and is implemented in a $0.18-{\mu}m$ CMOS technology. The proposed UWB LNA provides excellent wideband characteristics by combining a High-Pass Filter (HPF) with a conventional resistive-loaded LNA topology. In the proposed UWB LNA, the bell-shaped gain curve of the overall amplifier is much less dependent on the frequency response of the HPF embedded in the input stage. In addition, the adoption of fewer on-chip inductors in the input matching network permits a lower noise figure and a smaller chip area. Measurement results show a power gain of + 10 dB and an input return loss of more than - 9 dB over 2.7 to 6.2 GHz, a noise figure of 3.1 dB at 3.6 GHz and 7.8 dB at 6.2 GHz, an input PldB of - 12 dBm, and an IIP3 of - 0.2 dBm, while dissipating only 4.6 mA from a 1.8-V supply.

Automatic Generation of 3-D Finite Element Meshes: Part(II) -Mesh Generation from Tetrahedron-based Octree- (삼차원 유한요소의 자동생성 (2) -사면체 옥트리로부터의 유한요소 생성-)

  • 정융호;이건우
    • Transactions of the Korean Society of Mechanical Engineers
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    • v.19 no.3
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    • pp.647-660
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    • 1995
  • Given the tetrahedron-based octree approximation of a solid as described in part(I) of this thesis, in this part(II) a systematic procedure of 'boundary moving' is developed for the fully automatic generation of 3D finite element meshes. The algorithm moves some vertices of the octants near the boundary onto the exact surface of a solid without transforming the topology of octree leaf elements. As a result, the inner octree leaf elements can be used as exact tetrahedral finite element meshes. In addition, as a quality measure of a tetrahedral element, 'shape value' is propopsed and used for the generation of better finite elements during the boundary moving process.

A study on the fabrication techologies for the 23GHz LNAs (23GHz대 저잡음 증폭기의 제작기술에 관한 연구)

  • 안동식;장동표
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.34D no.3
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    • pp.9-16
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    • 1997
  • A 23GHz 1-stage LNA was designed by using new topology of coupled line type with EEsof softwares and modified by using MPIE numerical analysis. The parallel coupled filter-type matching sections give impedance matching and DC blocking simultaneously, and have small discontinuities. This matching scheme has simple structure in the design process and give small error. The EFT chip was directly attached to the ground metal. The designed LAN gives 6.2dB gain and 2.5dB noise figure without considering the loss of connectors. Through these results, it was verified that our design process, matching schemes and fabrication technologies was valied for developing 20GHz-band LNA.

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