• 전자공학회논문지A
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• 제33A권2호
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• pp.32-39
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• 1996

Hybrid decision decoding for the extended hamming codes without retransmission, which is a combination of hard and soft decision decoding, is proposed and its performance is analyzed in this paper. As results, hybsrid decision decoding shows a little bit higher residual bit error rate than soft decision decoding. However, as the size of the extended hamming code increases, the difference of th enumber of comparisons increases further. In addition, hybrid decision decoding shows almost same residual bit error rate as hard decision decoding with retrassmission and shows much lower residual bit error rate than hard decision decoding without retransmission.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.21-24
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• 2000

This paper introduces the design and implementation of a Ku-band 5-bit monolithic phase shifter with a ceramic package. The 5-bit phase shifter MMIC was designed and fabricated by using GaAs MESFET switches. The packaged phase shifter demonstrates a phase error less than 11.3 $^{\circ}$ RMS and an insertion loss variation less than 1.0㏈ RMS for 13∼15㎓. For all 32 states, an insertion loss is measured to be 12.2${\pm}$2.2㏈, an input return loss more than 5.0㏈, and an output return loss more than 6.2㏈ from 13㎓ to 15㎓. The chip size of the 5-bit phase shifter MMIC is 2.35${\times}$1.65mm$\^$2/ including digital control circuits. The size of the ceramic packaged phase shifter is 7.2${\times}$6.2mm$\^$2/.

• 대한전자공학회논문지
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• 제27권6호
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• pp.901-909
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• 1990

With a wide spread of 32 bit personal computers, a simple structure and high performance memory system have been highly required. In this paper, a memory block is constructed by using a modified hierarchical bit line in which the DRAM bit line and the latch which works as a SRAM cell are integrated by an interface gate. And the new architecture memory DSRAM(Dynamic Static RAM) is proposed by interleaving the 16 memory block. Because the DSRAM works with 16 page, the page is miss ratio becomes small and the RAS precharge time which is incurred by page miss is shortened. So the DSRAM can implement an optimum page interleaving and it has good compatibility to the existing DRAMs. The DSRAM can be widely used in small computers as well as a high performance memory system.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1987년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 16-17 Oct. 1987
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• pp.10-13
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• 1987

The main work of this paper are the manufacture of six degree of freedom industrial robot control hardware of 16 bit CPU and the development of five motion control software. The work would draw on KIT of Robotics Laboratory whose extensive experience in these areas; in particular the 68000 assembler and Modula-2 languages, and existing robot control systems. We found that this controller is good for the robot controller of PID types. But, for the use of self-tuning algorithms and real time calculations we need 32 bit CPU robot controller such as MC 68020 microprocessor.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 D
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• pp.2534-2536
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• 2002

This paper presents the design of high speed bit and word processor for sequence logic control using a FPGA. This FPGA is able to execute sequence instruction during program fetch cycle, because the program memory was separated from the data memory for high speed execution at 40MHz clock. Also this processor has 274 instructions set with a 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by V600EHQ240 and Foundation tool of Xilinx company. The final simulation was successfully performed under Foundation tool simulation environment. And the FPGA programmed by VHDL for a 240 pin HQFP package. Finally the benchmark was performed to prove that the designed for bit and word processor has better performance than Q4A of Mitsubishi for the sequence logic control.

• ETRI Journal
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• 제32권3호
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• pp.464-467
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• 2010

In this letter, we analyze the error performance of a mobile communication system with microdiversity and macrodiversity reception in gamma-shadowed Rician fading channels for a binary differential phase-shift keying modulation scheme. Analytical expressions for the probability density function (PDF) and moment-generating function (MGF) are derived. The average bit error probability can be calculated by averaging the conditional bit error probability over the PDF or using the MGF-based approach. Numerical results are graphically presented to show the effects of macrodiversity, correlation, number of diversity branches, and severity of both fading and shadowing.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(4)
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• pp.29-32
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• 2002

In typical block-based video coding, the objective of RC(Rate Control) is to select the quantization parameters so that the encoder produces bits at the rate of the channel and the overall distortion is minimized. To reduce the huge amount of computations required for offline RC, there have been significant efforts to speed up the process of video encoders. Those efforts have been mainly focused on the modes for bit rate and distortion in types of coders, in terms of the quantization parameters. Because previous works related to model based online RC are based on statistics of previous frame, it occurs the problem such that allocates bits unequally without regard to current frame statistics. In this thesis, an equal bit allocation scheme using current frame statistics is proposed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1984-1987
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• 2002

This paper describes the design and implementation of a single-chip digitally synthesized 0-35MHz agile function generator. The chip comprises an integrated direct digital synthesizer (DDS) with a 10-bit on- chip digital-to-analog converter (DAC) using an n-well single-poly triple-metal 0.5-$\mu\textrm{m}$ CMOS technology. The main features of the chip include maximum clock frequency of 100 MHz at 3.3-V supply voltage, 32-bit frequency tuning word resolution, 12-bit phase tuning word resolution, and an on-chip 10-bit DAC. The chip provides sinusoidal, ramp, saw-tooth, and random waveforms with phase and frequency modulation, and power-down function. At 100-MHz clock frequency, the chip covers a bandwidth from dc to 35 MHz in 0.0233-Hz frequency steps with 190-ns frequency switching speed. The complete chip occupies 12-mm$^2$die area and dissipates 0.4 W at 100-MHz clock frequency.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권1호
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• pp.23-32
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• 2011

A 40 fJ/c-s, 1 V, 10-bit SAR ADC is presented for energy constrained wearable body sensor network application. The proposed 10-bit dual sampling capacitive DAC topology reduces switching energy by 62% compared with 10-bit conventional SAR ADC. Also, it is more robust to capacitor mismatch than the conventional architecture due to its cancelling effect of each capacitive DAC. The proposed SAR ADC is fabricated in 0.18 ${\mu}m$ 1P6M CMOS technology and occupies 1.17 $mm^2$ including pads. It dissipates only 1.1 ${\mu}W$ with 1 V supply voltage while operating at 100 kS/s.

• 한국통신학회논문지
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• 제32권1C호
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• pp.16-22
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• 2007

본 논문에서는 선형계수확장 기반의 웨이블릿 워터마킹 기법을 제안하였다. 워터마크의 안정성을 위해 먼저 워터마크에 대해 Arnold 변환을 한 후, 선형계수확장을 적용하여 확대된 워터마크를 웨이블릿 변환 된 영상의 저주파대에 일정한 강도로 삽입하였으며 추출 시에는 기존 방법과 달리 F-노름(norm) 함수를 적용하였다. 실험결과 본 논문에서 제안한 방법은 충실도와 강인성 측면에서 우수한 특성을 가짐을 확인하였다.