• Journal of the Korean Society of Industry Convergence
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• v.23 no.6_2
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• pp.989-998
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• 2020

Recently, demands for large-capacity electronic loads are increasing in various industries such as a reliability test for the performance of a DC power supply device or a dummy-load for improving the stability of an independent microgrid to be actively built in the future. The electronic load required in these various fields requires an operation such as a continuously variable resistance load while minimizing the switching harmonic component generated in the electric load current in order to reduce the influence of interference from the load peripheral device. Electronic loads require a system that minimizes switching current ripple for load control. Therefore, in this paper, we propose a three-level module converter structure to reduce the current ripple of an electronic load, and a multilevel interleaved power converter topology to reduce the current ripple. The validity of the proposed electronic load, 3-level 6 interleaver converter, was verified by simulation and experiment. In addition, the user's convenience was provided by applying the emotional command curve interface method.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.448-451
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• 2000

This paper proposed a snubber circuit for flying capacitor multilevel inverter and converter. The proposed snubber circuit makes use of Undeland snubber as basic snubber as basic snubber unit and has such an advantage of Undeland snubber used in the two-level inverter. Comparing conventional RCD/RLD snubber for multilevel in verter and converter the proposed snubber keeps such a good features as fewer number of components improved efficiency of system due to low loss snubber and reduction of voltage stress of main switching devices due to low overvoltage. Furthermore the proposed concept of constructing a snubber circuit for flying capacitor 3-level inverter and converter can apply to any level of them. In this paper the proposed snubber applies to three-level flying capacitor inverter and demonstrates its feature by computer simulation and experimental result.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.3
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• pp.391-396
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• 2012

The Voltage Bus Conditioner(VBC) is a bidirectional DC-DC converter for damping the instability and any transients of the bus voltage in a DC Distributed Power System(DPS). In this paper, a PI controller for the VBC has been designed for the frequency domain. The proposed PI controller not only dampens the bus transients, but also keeps the storage voltage level. Simulation by Matlab/Simulink and experimental results are presented for the validity of the proposed control technique.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.5
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• pp.336-344
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• 2018

This study proposes a new PWM method for leakage current reduction and neutral point (NP) current control in three-phase three-level converter employed in bipolar DC distribution systems. The proposed PWM method uses medium vectors only when there is no need to control the NP current. Thus, common mode voltages are held constant to realize zero leakage current. Some space vectors that produce low-frequency common mode voltages are employed to minimize leakage currents when the average NP current needs to be a positive or negative value. The proposed space vector PWM is implemented based on barycentric coordinate. The validity of the proposed PWM method is verified by simulations and experiments.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.300-311
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• 2016

The analog-to-digital-converter-based (ADC-based) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both front-end ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.4
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• pp.380-387
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• 2005

We report the performance of an open-frame type low-voltage high-current DC-DC converter module developed using an active clamp forward converter circuit and single ended rectifier. The converter module is designed with the specifications of an 3.3V output voltage, 30A output current, 100W output power and 36-75V input voltage. The synchronous rectifier is used to reduce the conduction loss at high current level and constant current control using precision PCB resistance is adapted to enhance the over current protection function in the system configuration. A prototype converter module is successfully implemented within 8mm height and quarter brick size (58x37mm) and recorded an $95W/in^3$ power density, 90.6$\%$ efficiency and 0.07$\%$ voltage regulation for the entire Input voltage range, thereby demonstrating its application potentials to future telecommunication electronics.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.361-362
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• 2015

This paper proposes a Direct Power Control (DPC) scheme of improved command tracking capability for Permanent Magnet Synchronous Generator (PMSG) Medium Voltage (MV) Wind Turbines. Benchmarking is performed based on a neutral point clamped three-level back-to-back type voltage source converter. It is introduced to design the DPC modeling and propose DPC scheme of a three-level NPC (3L-NPC) converter. During the fault condition in wind farms, the proposed control scheme directly controls the generated output power to the command value from the hierarchical wind farm controller. The proposed control scheme is compared with conventional control scheme as respect to loss and thermal analysis. The DPC scheme of improved command tracking capability is confirmed through PLECS simulations. Simulation result shows that proposed control scheme achieves a much shorter transient time in a step response of generated output power. The proposed control scheme makes it possible to provide a good dynamic performance for PMSG MV wind turbine to generate a high quality output power under grid fault condition.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• Journal of Power Electronics
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• v.14 no.3
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• pp.507-518
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• 2014

This paper presents a new cascaded asymmetrical single phase multilevel converter with a lower number of power semiconductor switches and isolated DC sources. Therefore, the number of power electronic devices, converter losses, size, and cost are reduced. The proposed multilevel converter topology consists of two H-bridges connected in cascaded configuration. One H-bridge operates at a high frequency (high frequency inverter) and is capable of developing a two level output while the other H-bridge operates at the fundamental frequency (low frequency inverter) and is capable of developing a multilevel output. The addition of each power electronic switch to the low frequency inverter increases the number of levels by four. This paper also introduces a hybrid switching algorithm which uses very simple arithmetic and logical operations. The simplified hybrid switching algorithm is generalized for any number of levels. The proposed simplified switching algorithm is developed using a TMS320F2812 DSP board. The operation and performance of the proposed multilevel converter are verified by simulations using MATLAB/SIMULINK and experimental results.

• Journal of Power Electronics
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• v.1 no.2
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• pp.107-116
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• 2001

Two AC-DC PWM full-bridge converters that can input current to improve input power factor while performing dc-dc conversion are investigated in this paper. Both converters are simple in that they are similar to the standard PWM full-bridge converter with a diode rectifier/LC low-pass filter input, and both can operate with a simple method of PWM control. In the paper, the operation of the converters is explained and their steady-state characteristics are discussed. The feasibility of the converters and their ability to meet EN61000-3-2 Class D Standards for electrical equipment are shown with results obtained from experimental prototypes. The performance of both converters in terms of dc bus voltage level, input power factor and efficiency is compared and discussed.