• 제목/요약/키워드: 3-level power converter

검색결과 227건 처리시간 0.025초

Rapid Electric Vehicle Charging System with Enhanced V2G Performance

  • Kang, Taewon;Kim, Changwoo;Suh, Yongsug;Park, Hyeoncheol;Kang, Byungik;Kim, Simon
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2012년도 전력전자학술대회 논문집
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    • pp.201-202
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    • 2012
  • This paper presents a simple and cost-effective stand-alone rapid battery charging system of 30kW for electric vehicles. The proposed system mainly consists of active front-end rectifier of neutral point clamped 3-level type and non-isolated bi-directional dc-dc converter of multi-phase interleaved half-bridge topology. The charging system is designed to operate for both lithium-polymer and lithium-ion batteries. The complete charging sequence is made up of three sub-interval operating modes; pre-charging mode, constant-current mode, and constant-voltage mode. Each mode is operated according to battery states: voltage, current and State of Charging (SOC). The proposed system is able to reach the full-charge state within less than 16min for the battery capacity of 8kWh by supplying the charging current of 67A. The optimal discharging algorithm for Vehicle to the Grid (V2G) operation has been adopted to maintain the discharging current of 1C. Owing to the simple and compact power conversion scheme, the proposed solution has superior module-friendly mechanical structure which is absolutely required to realize flexible power expansion capability in a very high-current rapid charging system. Experiment waveforms confirm the proposed functionality of the charging system.

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효율적인 주파수 변조된 초음파 파형 발생을 위한 최적화된 시그마 델타 변조 기법 (Optimized Sigma-Delta Modulation Methodology for an Effective FM Waveform Generation in the Ultrasound System)

  • 김학현;한호산;송태경
    • 대한의용생체공학회:의공학회지
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    • 제28권3호
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    • pp.429-440
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    • 2007
  • A coded excitation has been studied to improve the performance for ultrasound imaging in term of SNR, imaging frame rate, contrast to tissue ratio, and so forth. However, it requires a complicated arbitrary waveform transmitter for each active channel that is typically composed of a multi-bit Digital-to-Analog Converter (DAC) and a linear power amplifier (LPA). Not only does the LPA increase the cost and size of a transmitter block, but it consumes much power, increasing the system complexity further and causing a heating-up problem. This paper proposes an optimized 1.5bit fourth order sigma-delta modulation technique applicable to design an efficient arbitrary waveform generator with greatly reduced power dissipation and hardware. The proposed SDM can provide a required SQNR with a low over-sampling ratio of 4. To this end, the loop coefficients are optimized to minimize the quantization noise power in signal band while maintaining system stability. In addition, the decision level for the 1.5 bit quantizer is optimized for a given input waveform, which results in the SQNR improvement of more than 5dB. Computer simulation results show that the SQNR of a FM(frequency modulated) signal generated by using the proposed method is about 26dB, and the peak side-lobe level (PSL) of its compressed waveform on receive is -48dB.

태양광 분산형 최대전력점 추적 제어를 위한 고전압 게이트 드라이버 설계 (A Design of Gate Driver Circuits in DMPPT Control for Photovoltaic System)

  • 김민기;임신일
    • 한국산업정보학회논문지
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    • 제19권3호
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    • pp.25-30
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    • 2014
  • 본 논문에서는 태양광시스템의 분산형 최대 전력점 추적(DMPPT)을 제어하는 게이트 드라이버 회로를 설계하였다. 그림자가 생긴 모듈에서도 최대 전력점을 추적할 수 있는 분산형 방식(DMPPT) 방식을 구현 하였으며, 각각의 모듈 내부에 DC-DC 변환기를 구동하기 위한 고전압 게이트 구동회로를 설계하였다. 태양광 시스템의 내부는 12비트 ADC, PLL, 게이트 드라이버가 내장 되어 있다. 게이트 드라이버의 하이 사이드 레벨 쉬프터에 숏-펄스 발생기를 추가하여 전력소모와 소자가 받는 스트레스를 줄였다. BCDMOS 0.35um 공정을 사용하여 구현하였으며 최대 2A 전류를 감달 할 수 있고, 태양 광 전압 최대 50V까지 받을 수 있도록 설계하였다.

태양광 발전 시스템의 무순단 MPPT 운전 모드 절체 기법 (Seamless Transfer Method of MPPT for Two-stage Photovoltaic PCS)

  • 박종화;조종민;안현성;차한주
    • 전기학회논문지
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    • 제67권2호
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    • pp.233-238
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    • 2018
  • This paper proposes a seamless MPPT operation mode transfer method of photovoltaic system. The photovoltaic system consists of a DC-DC boost converter, a DC-Link, and a 3-level neutral point clamp (NPC) type inverter. The PV voltage fluctuates due to the output characteristics of the solar pane1 depending on the irradiation amount and the temperature. The photovoltaic system requires seamless MPPT mode transfer method that the discontinuity does not occur in order to supply the stable power to system without affecting the fluctuation of the PV voltage. MPPT operation is divided into two modes by the voltage reference. Under the condition that the PV voltage is below 650V, the DC-DC boost converter performs MPPT through duty control based on perturb & observe (P&O) method, and the inverter conducts DC-link voltage and grid current controls in synchronous reference frame. On the other hand, when the PV voltage exceeds above 650V, inverter performs MPPT in accordance with the variation of DC-link voltage control while the converter stops operating. Two MPPT operation modes is smoothly transferred through the proposed method that DC-link voltage or grid current commands are appropriately adjusted from the certain criteria. The feasibility of the MPPT operation mode transfer method is verified using a 10kW solar photovoltaic system, experimental results have good performances that the fluctuation of PV current is reduced to 100%.

Fuzzy Logic PID controller based on FPGA

  • Tipsuwanporn, V.;Runghimmawan, T.;Krongratana, V.;Suesut, T.;Jitnaknan, P.
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2003년도 ICCAS
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    • pp.1066-1070
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    • 2003
  • Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

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Fault Current Limitation by a Superconducting Coil with a Reversely Magnetized Core for a Fault Current Controller

  • Ahn, Min Cheol;Ko, Tae Kuk
    • 한국초전도ㆍ저온공학회논문지
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    • 제14권4호
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    • pp.36-40
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    • 2012
  • This paper presents an experimental and numerical study on current limiting characteristics of a fault current controller (FCC). The FCC consists of an AC/DC power converter, a superconducting coil, and a control unit. Even though some previous researches proved that the FCC could adjust the fault current level, the current limiting characteristics by the superconducting coil should be investigated for design of the coil. In this paper, four kinds of model coils were tested; 1) air core, 2) iron core without any bias, 3) reversely magnetized core (RMC) using permanent magnets, and 4) RMC using an electromagnet. Based on a comparative study, it is confirmed that a RMC by an electromagnet (EM) could increase the effective inductance of the coil. In this paper, a numerical code to simulate the HTS coil with RMC was developed. This code can be applied to design the HTS coil with active reversely magnetized bias coil.

IC-임베디드 PCB 공정을 사용한 DVB-T/H SiP 설계 (Design of DVB-T/H SiP using IC-embedded PCB Process)

  • 이태헌;이장훈;윤영민;최석문;김창균;송인채;김부균;위재경
    • 대한전자공학회논문지SD
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    • 제47권9호
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    • pp.14-23
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    • 2010
  • 본 논문에서는 유럽에서 사용되는 이동형 디지털 방송인 DVB-T/H 신호를 수신 및 신호처리 가능한 DVB-T/H SiP를 제작하였다. DVB-T/H SiP는 칩이 PCB 내부에 삽입될 수 있는 IC-임베디드 PCB 공정을 적용하여 설계되었다. DVB-T/H SiP에 삽입된 DVB-T/H IC는 신호를 수신하는 RF 칩과 어플리케이션 프로세서에서 활용할 수 있도록 수신된 신호를 변환하는 디지털 칩 2개를 원칩화한 모바일 TV용 SoC 이다. SiP 에는 DVB-T/H IC를 동작하기 위해 클럭소스로써 38.4MHz의 크리스탈을 이용하고, 전원공급을 위해 3MHz로 동작하는 DC-DC Converter와 LDO를 사용하였다. 제작된 DVB-T/H SiP는 $8mm{\times}8mm$ 의 4 Layer로 구성되었으며, IC-임베디드 PCB 기술을 사용하여 DVB-T/H IC는 2층과 3층에 배치시켰다. 시뮬레이션 결과 Ground Plane과 비아의 확보로 RF 신호선의 감도가 개선되었으며 SiP로 제작하는 경우에 Power 전달선에 존재하는 캐패시터와 인덕터의 조정이 필수적임을 확인하였다. 제작된 DVB-T/H SiP의 전력 소모는 평균 297mW이며 전력 효율은 87%로써 기존 모듈과 동등한 수준으로 구현되었고, 크기는 기존 모듈과 비교하여 70% 이상 감소하였다. 그러나 기존 모듈 대비평균 3.8dB의 수신 감도 하락이 나타났다. 이는 SiP에 존재하는 DC-DC Converter의 노이즈로 인한 2.8dB의 신호 감도 저하에 기인한 것이다.

A Study on Single-bit Feedback Multi-bit Sigma Delta A/D converter for improving nonlinearity

  • Kim, Hwa-Young;Ryu, Jang-Woo;Jung, Min-Chul;Sung, Man-Young
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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    • pp.57-60
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    • 2004
  • This paper presents multibit Sigma-Delta ADC using Leslie-Singh Structure to Improve nonlinearity of feedback loop. 4-bit flash ADC for multibit Quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. Thus a Sigma-Delta ADC usually adds the dynamic element matching digital circuit within feedback loop. It occurs complexity of Sigma-Delta Circuit and increase of power dissipation. In this paper using the Leslie-Singh Structure for improving nonliearity of ADC. This structure operate at low oversampling ratio but is difficult to achieve high resolution. So in this paper propose improving loop filter for single-bit feedback multi-bit quantization Sigma-Delta ADC. It obtained 94.3dB signal to noise ratio over 615kHz bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is fabricated in 0.25um CMOS technology with 2.5V supply voltage.

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SoC 기반 보급형 MiC 스마트 태양광발전시스템 기술개발 (Technology Development of Entry-Level MiC Smart Photovoltaic System based on SOC)

  • 윤용호
    • 한국인터넷방송통신학회논문지
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    • 제20권3호
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    • pp.129-134
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    • 2020
  • 최근 태양전지 모듈 내부에 습기 침투 및 EVA Sheet의 배부름 현상, 프레임 Seal이 녹아내리는 현상, 설치 후 1년 지난 모듈에서 발전성능이 저하되는 현상 등이 발생하고 있다. 국내에 5~7년 이전에 설치된 태양전지 모듈에서 백화현상 및 전극 부식 현상, 절연파괴 현상 등이 나타나기 시작하여 발전성능 저하로 이어지고, 장기 신뢰성 및 장수명 기술에 대한 커다란 문제점이 대두되고 있다. 따라서 이러한 문제점들을 해결하기 위해 태양전지 모듈의 내구성 확보 및 노화 진행을 모니터링할 수 있는 기능을 포함하는 마이크로 인버터 (MiCrco Inverter Converter, 이하 MiC) 개발 및 MiC에서 모니터링 데이터를 기반으로 태양전지 모듈의 노화를 판단할 수 있는 스마트 모니터링 프로그램이 제시되고 있다. 또한, 태양전지 모듈의 모니터링 기능을 강화한 MiC와 IT 융합을 통한 체계적 운영 관리를 통한 고효율 태양광 스마트 감시 시스템이 되기 위해서는 MiC 내의 SoC (System On Chip)는 태양전지 모듈에 대한 환경정보를 복합적으로 감지하고 필요시 통신 및 제어를 수행할 수 있는 기능들이 요구되고 있다. 이러한 요구사항들을 기반으로 본 논문에서는 SoC 기반 보급형 MIC 스마트 태양광발전시스템 기술개발을 목적으로 연구하고자 한다.

The Effect of Image Rejection Filter on Flatness of Microwave Terrestrial Receiver

  • Han, Sok-Kyun;Park, Byung-Ha
    • Journal of electromagnetic engineering and science
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    • 제3권2호
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    • pp.86-90
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    • 2003
  • A flat conversion loss in microwave mixer is hard to achieve if integrating with an image rejection filter(IRF). This is due to the change of termination condition with respect to the LO and IF frequency at RF port where the filter has 50 ohm termination property only in the RF band. This paper describes a flatness maintenance in the down mixer concerning a diode matching condition as well as an electrical length of embedding line at RF port. The implemented single balance diode mixer is suitable for a 23 ㎓ European Terrestrial Radio. RF, LO and fixed IF frequency chosen in this paper are 21.2∼22.4 ㎓, 22.4∼23.6 ㎓ and 1.2 ㎓, respectively. The measured results show a conversion loss of 8.5 ㏈, flatness of 1.2 ㏈ p-p, input P1㏈ of 7㏈m, IIP3 of 15.42 ㏈m with nominal LO power level of 10㏈m. The return loss of RF and LO port are less than - 15 ㏈ and - 12 ㏈, respectively and IF port is less than - 6 ㏈. LO/RF and LO/IF isolation are 18 ㏈ and 50 ㏈, respectively. This approach would be a helpful reference for designing up/down converter possessing a filtering element.