• Journal of Electrical Engineering and Technology
• /
• v.12 no.1
• /
• pp.100-109
• /
• 2017

This paper proposes performance improvement schemes for sensorless PMSM control drive using a four-switch three-phase inverter (so-called B4 inverter). In the proposed scheme, the back-EMF estimation-based sensorless control algorithm is used to control the brushless PMSM without position sensors. In order to have stable operation, this paper presents a gain adjustment scheme that compensates the reduction of stable sensorless operation range as long as the rotor speed increases. In B4 topology, the center point of dc-link capacitors is connected to 3-phase load, and it is prone to have the load current distortion. Hence, to mitigate this problem, a distortion compensation scheme by modifying voltage commands using measured dc-link potentials is proposed in this paper. The validity of the proposed method is evaluated by simulations and experiments.

• Proceedings of the KIEE Conference
• /
• 1991.07a
• /
• pp.568-572
• /
• 1991

This paper describes the three-phase inverter system for 1/2[HP] induction servo motor, using TMS370C050 single-chip microprocessor. The Power MOSFETs are used for PWM inverter circuit because of the advantages such as less harmonic losses and smaller peak current, less torque ripples and noises. Single-chip microprocessor enables the whole controller to be simple and reduced size as well as to more stable and flexible. The basic structures are shown for the power circuit, including the protection and driving circuitry, and the control loops for inverter control functions. The experimental results are given for the prototype PWM inverter system.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.40 no.5
• /
• pp.479-488
• /
• 1991

A novel three-phase quasi-resonant dc link inverter (QRI)with a switch connected between dc voltage source and resonant inductor is proposed. According to the state of switching and load current, the operating mode of the proposed inverter scheme is classified into free-wheeling, inverting, and rectifying mode. By examining the behavior of the circuit in each operating mode, an equivalent circuit which represents all the modes in a unified manner is derived. The operating principle of QRI at inverting mode is analyzed, and it is shown that the maximum voltage of resonant dc link is confined to twice the dc source voltage and that both the zero voltage switching of inverter and the zero current switching of inserted switch are guaranteed. An appropriate current control algorithm is suggested, and the opeating characteristics of proposed resonant inverter are verified through both simulation and experiment.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.62 no.11
• /
• pp.1560-1565
• /
• 2013

This paper proposes the control method for compensating for unbalanced grid current and reducing a total harmonic distortion (THD) of the grid current at the three-phase grid-connected inverter systems under unbalancd and distorted grid voltage conditions. The THD of the grid current caused by grid voltage harmonics is derived by considering the phase delay and magnitude attenuation due to the hardware low-pass filter (LPF). The Cauchy-Schwarz inequality theory is used in order to search more easily for a minimum point of THD. Both the gain and angle of a compensation voltage at the minimum point of THD of the grid current are derived. The negative-sequence components in the three-phase unbalanced grid voltage are cancelled in order to achieve the balanced grid current. The simulation and experimental results show the validity of the proposed control methods.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.25 no.3
• /
• pp.235-241
• /
• 2020

In this paper, we propose the bus/bypass synchronization phase lock loop (B-Sync PLL) method using each phase voltage controller of a parallel UPS inverter. The B-Sync PLL included in each phase voltage control system of parallel UPS inverters has the transient response and the phase synchronization error at grid normal or blackout. The validity of this method is verified by simulation and experiment. As a result, the parallel UPS inverters using the proposed method confirmed that the output phase was continuously synchronized when a grid blackout, improving the transient response characteristics for stable load power supply and equal load sharing.

• Proceedings of the KIPE Conference
• /
• 2015.11a
• /
• pp.151-152
• /
• 2015

This paper is research on design controller of grid connected 3-phase inverter. It confirms effects of high harmonics on controller and imposes repetitive controller to minimize effects on the high harmonics. The result of test in this paper is drawn by simulation tool.

• Proceedings of the KIEE Conference
• /
• 1994.07a
• /
• pp.565-567
• /
• 1994

This paper presents a software based NPC PWM inverter control technique to eliminate the harmonics in the output waveforms of inverter. The proposed control technique is able to keep down total harmonic distortion and significantly improve the performance of the inverter. In the control node where the frequency ratio is 36 and the modulation index is $1.2\sim2.0$, the proposed inverter has been operated wi thin 5% Total Harmonic Distortion.

• Journal of Power Electronics
• /
• v.17 no.1
• /
• pp.115-126
• /
• 2017

This paper presents a new cascaded asymmetrical single phase multilevel converter with a reduced number of isolated DC sources and power semiconductor switches. The proposed inverter has only two H-bridges connected in cascade, one switching at a high frequency and the other switching at a low frequency. The Low Switching Frequency Inverter (LSFI) generates seven levels whereas the High Switching Frequency Inverter (HSFI) generates only two levels. This paper also presents a solution to the capacitor balancing issues of the LSFI. The proposed inverter has lot of advantages such as reductions in the number of DC sources, switching losses, power electronic devices, size and cost. The proposed inverter with a capacitor voltage balancing algorithm is simulated using MATLAB/SIMULINK. The switching logic of the proposed inverter with a capacitor voltage balancing algorithm is developed using a FPGA SPATRAN 3A DSP board. A laboratory prototype is built to validate the simulation results.

• International Journal of Control, Automation, and Systems
• /
• v.3 no.4
• /
• pp.620-630
• /
• 2005

This paper presents a digital controller for a single phase UPS inverter under two main considerations: (i) the overall system shall keep very low AC-voltage tracking error as well as no phase delay over different load conditions, and (ii) the digital controller shall be employed at a fixed sampling time. We propose that the former can be achieved by the proposed controller using the error-state approach and the latter can be dealt with by the socalled characteristics ration assignment.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.26 no.3
• /
• pp.176-182
• /
• 2021

This research proposes a high-frequency circuit that can accurately predict the differential mode noise of single-phase inverters at the circuit design stage. Proposed single-phase inverter high frequency circuit in the work is a form in which harmonic impedance components are added to the basic single-phase inverter circuit configuration. For accurate noise prediction, parasitic components present in each part of the differential noise path were extracted. Impedance was extracted using a network analyzer and Q3D in the measurement range of 150 kHz to 30 MHz. A high-frequency circuit model was completed by applying the measured values. Simulations and experiments were conducted to confirm the validity of the high-frequency circuit. As a result, we were able to predict the resonance point of the differential mode voltage extracted as an experimental value with a high-frequency circuit model within an approximately 10% error. Through this outcome, we could verify that differential mode noise can be accurately predicted using the proposed model of the high-frequency circuit without a separate test bench for noise measurement.