• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.3
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• pp.244-252
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• 2002

In this paper, do link ripple currents for three-phase ac/dc/ac PWM converters feeding adjustable speed ac machine drives are analysed in a frequency domain. The expression of the harmonic currents is developed by using switching functions of the converter and exponential courier series expansion. The effect of the displacement angle between the switching Periods of line-side converters and motor-side inverters on the dc link ripple currents is Investigated. Also, the influence of asynchronization of PWM is observed. The result of analysis is compared with frequency spectrum which results from PSIM simulation. The proposed analysis technique is useful to understand the principles of P% and to derive an equivalent model of the dc link capacitors in a high frequency range.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.441-443
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• 2007

In this paper, The authors design the current controller which independently control the d, q axis current transformed by the synchronously rotating d, q axis and a Space Vector Pulse Width Modulation(SVPWM) to steadily control the output DC-Link voltage against the variable load of the three phase PWM converter. Also, This study improves the high power factor, stability, and rapid response by the phase angle control using the digital Phase Locked Loop(PLL).

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.218-219
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• 2016

This paper present Phase Shifted with carrier based on Sinusoidal PWM(SPWM) by using Cascaded NPC/H-birdge converter. The proposed Phase Shifted PWM method is adding third harmonic injection in switching signal. The advantage of the proposed method is reducing the voltage and capacity of the capacitor. This paper compare general Phase Shifted method with proposed Phase Shifted method that added the third harmonic injection. Each PWM method is tested without considering the switching loss by using PSIM 9.1.4 simulation.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.11a
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• pp.387-390
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• 2005

A This paper presents a novel three-phase current-fed Pulse Width Modulation converter with switched- capacitor type resonant DC link commutation circuit operating PWM pattern strategy under a design consideration of low-pass filter, which can operate on the basis of the principle of zero current soft-switching commutation. In the first place, the steady-state operating principle of this converter with a new resonant DC link snubber circuit is described in connection with the equivalent operation circuit, together with the practical design procedure of the switched-capacitor type resonant DC link circuit is discussed from a theoretical viewpoint on the basis of a design example for high-power applications. The actively delayed time correction method to compensate distorted currents due to a relatively long resonant commutation time is newly implemented in the open loop control scheme so as to acquire the new optimum PWM pattern. Finally, the experiment or set-up in laboratory system or this converter is concretely demonstrated herein to confirm a zero current soft-switching commutation of this converter. The comparative evaluations between current-fed hard switching PWM and soft-switching PWM converters are carried out from a viewpoint of their PWM converter characteristics.

• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.345-351
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• 1997

In this paper, controller for PWM converter considering unsymetrical input voltage is designed and current controller using LQ controller with conditional integrator is proposed. And the proposed current controller is compared with other current controller-predictive controller, decoupling PI controller. As simulation results, LQ controller with Conditional Integrator shows the improved performance for DC link voltage regulation through transient test of load variation. And when unsymeritrical input voltage is applied to converter with conventional current controller considering only symetrical input voltage, input current is distorted but it is showed that current controller considering unsymetrical input has robust control characteristics under phase voltage unbalance.

• Journal of Power Electronics
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• v.15 no.3
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• pp.652-659
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• 2015

This paper presents a new hybrid soft switching dc-dc converter with a low circulating current and high circuit efficiency. The proposed hybrid converter includes two sub-converters sharing two power switches. One is a three-level PWM converter and the other is a LLC converter. The LLC converter and the three-level converter share the lagging-leg switches and extend the zero-voltage switching (ZVS) range of the lagging-leg switches from nearly zero to full load since the LLC converter can be operated at f_sw (switching frequency) $\approx$ f_r (series resonant frequency). A passive snubber is used on the secondary side of the three-level converter to decrease the circulating current on the primary side, especially at high input voltage and full load conditions. Thus, the conduction losses due to the circulating current are reduced. The output sides of the two converters are connected in series. Energy can be transferred from the input voltage to the output load within the whole switching period. Finally, the effectiveness of the proposed converter is verified by experiments with a 1.44kW prototype circuit.

• Journal of Power Electronics
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• v.14 no.3
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• pp.531-540
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• 2014

A novel carrier-based PWM (CBPWM) strategy of a three-level NPC converter is proposed in this paper. The novel strategy can eliminate the low-frequency neutral point (NP) voltage oscillation under the entire modulation index and full power factor. The basic principle of the novel strategy is introduced. The internal modulation wave relationship between the novel CBPWM strategy and traditional SPWM strategy is also studied. All 64 modulation wave solutions of the CBPWM strategy are derived. Furthermore, the proposed CBPWM strategy is compared with traditional SPWM strategy regarding the output phase voltage THD characteristics, DC voltage utilization ratio, and device switching losses. Comparison results show that the proposed strategy does not cause NP voltage oscillation. As a result, no low-frequency harmonics occur on output line-to-line voltage and phase current. The novel strategy also has higher DC voltage utilization ratio (15.47% higher than that of SPWM strategy), whereas it causes larger device switching losses (4/3 times of SPWM strategy). The effectiveness of the proposed modulation strategy is verified by simulation and experiment results.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.64-72
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• 2000

This paper deals with the parallel operation of two PWM converters for auxiliary block of high speed train. The parallel operation of AC/DC PWM converter controlled by 3-level PWM switching method to operate switching devices to realize a high power factor and reduce the primary side of the transformer current harmonics is proposed. In this paper, it is presented the phase shift technique between two converters switching phase, solution to eliminate the coupling effects due to the transformer and zero crossing detection method for synchronized with the source and controller. Experimental results for laboratory system with TMS320C31 microprocessor and 10［kVA］PWM converter confirm the validity of the proposed algorithm.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.4
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• pp.375-387
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• 2015

This study investigates an economic and highly efficient power-converter topology and its modulation scheme for 60 kW rapid EV charger system. The target system is a three-phase three-switch buck-type rectifier topology. A new carrier-based PWM scheme, which is characterized by simple implementation using logic gates, is introduced in this paper. This PWM scheme replaces the diode rectifier equivalent switching state with an active switching state to produce the same effective current flowing path. As a result, the distortion of input current during the polarity reversal of capacitor line voltage can be mitigated. The proposed modulation technique is confirmed through simulation verification. The proposed modulation technique and its implementation scheme can expand the operation range of the three-phase three-switch buck-type rectifier with high-quality AC input and capacitor ripple current.