• 전기전자학회논문지
• /
• 제18권1호
• /
• pp.37-44
• /
• 2014

In this paper we present an LDO based on an error amplifier. The designed error amplifier has a gain of 89.93dB at low frequencies. This amplifier's Bandwidth is 50.8MHz and its phase margin is $59.2^{\circ}C$. Also we proposed a BGR. This BGR has a low output variation with temperature and its PSRR at 1 KHz is -71.5dB. For a temperature variation from $-40^{\circ}C$ to $125^{\circ}C$ we have just 9.4mV variation in 3.3V LDO output. Also it is stable for a wide range of output load currents [0-200mA] and a $1{\mu}F$ output capacitor and its line regulation and especially load regulation is very small comparing other papers. The PSRR of proposed LDO is -61.16dB at 1 KHz. Also we designed it for several output voltages by using a ladder of resistors, transmission gates and a decoder. Low power consumption is the other superiority of this LDO which is just 1.55mW in full load. The circuit was designed in $0.35{\mu}m$ CMOS process.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1994년도 하계학술대회 논문집 C
• /
• pp.1577-1579
• /
• 1994

200-MW pulse modulators(total 11units) for the PLS linac employ the SCR phase control circuit. It controls 3-phase AC line voltage for the high-voltage DC power supply (DCPS, maximum of 25kVDC, 4.2A) which charges the pulse forming network(PFN). The PFN delivers 400kV, 500A, ESW $7.5{\mu}s$ pulse power to the 80-MW klystron amplifier tube. The SCR regulates 3-phase AC power and feeds to the high voltage transformer. Two different types of the transformer configurations namely ${\Delta}-{\Delta}$ and ${\Delta}-Y$, are alternatively installed to 11 modulator units for the suppression of harmonic noises. RC filters and reactors are also installed. Currently, approximately 110-kW of average AC power per unit is consumed at the normal operation level of the modulator with 30pps. This paper presents the operational characteristics of the high power pulse modulator, especially the experimental results of the AC line harmonic components generated by the operation of the high power pulse modulator to suppress the switching noises from the SCR and rectifying diode arrays.

• 한국군사과학기술학회지
• /
• 제11권3호
• /
• pp.146-153
• /
• 2008

High-power communication jammer has to include the switched filter bank to eliminate the harmonic signals generated by amplifier. Generally, the switched filter bank consists of in-out switches and several filters. This paper describes the design of high-power switched filter bank, particularly the high-power filter bank operating over 20$\sim$110MHz frequency range. The filters designed have insertion loss less than 0.3dB, VSWR less than 1.25:1, and harmonic suppression more than 35dB. Also, the switched filter bank can endure upto 2kW high-power signal with very low harmonic level within $30{\mu}s$ switching speed.

• 전자공학회논문지
• /
• 제51권4호
• /
• pp.49-58
• /
• 2014

본 논문에서는 저전력 고속 모바일 I/O 인터페이스를 위한 저스윙 차동 니어-그라운드 시그널링 (NGS) 트랜시버를 소개한다. 제안하는 트랜스미터는 온-칩 레귤레이터로 정류된 프로그래머블한 스윙을 가지는 전압-모드 드라이버와 비대칭 상승/하강시간을 가지는 전단드라이버를 사용한다. 제안하는 리시버는 고주파이득을 신장시키는 피드-포워드 커패시터를 이용한 새로운 다중경로이득 차동앰프를 사용한다. 또한, 이 리시버는 가변적인 트랜스미터 출력스윙에 의한 입력 공통모드 변화를 보상하며, 리시버 입력단 증폭기의 전류 미스매치를 최소화하기 위하여 새로운 적응형 바이어스 생성기를 포함한다. 트랜스미터와 리시버에 적용된 새로운 간단하고 효과적인 임피던스 매칭 기술들의 사용으로 우수한 시그널 인테그리티와 높은 파워 효율을 이뤄냈다. 65 nm CMOS 공정으로 설계된 제안하는 트랜시버는 10 cm 길이의 FR4 PCB에서 채널당 13 Gbps의 전송속도와 0.3 pJ/bit (= 0.3 mW/Gbps)의 높은 파워 효율을 갖는다.

• 한국군사과학기술학회지
• /
• 제19권5호
• /
• pp.574-581
• /
• 2016

Trend on high-power GaN(Gallium Nitride) SSPA(Solid-State Power Amplifier) and its availability in miniature radar systems are presented. There are numerous studies on high-power GaN devices since they have some characteristics of high-breakdown voltage, high power density, and high-temperature stability. Recent scaled GaN technology makes it possible to apply it in SSPAs for W- and G-band applications, with increasing its maximum frequency. In addition, it leads to downsizing and power-efficiency improvement of SSPAs, which means that GaN SSPAs can be available in miniature radar systems. This study also shows radar performance and comparison in the case of using such SSPAs at three frequency bands of Ku, Ka, and W. Finally, we demonstrate prospects of scaled GaN SSPAs in future miniature radar systems.

• 한국산학기술학회:학술대회논문집
• /
• 한국산학기술학회 2010년도 추계학술발표논문집 1부
• /
• pp.168-171
• /
• 2010

본 논문에서는 GaN HEMT 소자를 이용한 고출력 고효율 특성을 가지는 광대역 SSPA의 개발을 다루고 있다. 개발한 SSPA는 8W 급과 15W 급의 GaN HEMT 소자를 사용하여 Pre-Drive 증폭단을 구성하였으며, Drive 증폭단은 50W/150W급 GaN HEMT 소자를 직/병렬구조로 사용하였다. Main 증폭단은 4-way 분배기와 결합기를 이용한 Balanced Structure를 적용하여 높은 출력을 구현하였으며, 안정적인 동작을 위하여 음(-)전원 제어 회로와 출력신호 검출 회로를 포함하고 있다. 제작된 SSPA의 사용가능 대역은 2.9GHz~3.3GHz로 단일전원을 사용하고 있으며 100us 펄스 폭, 10% Duty Cycle 조건에서 60dB의 전압이득, 1kW 출력과 약 28% 효율 특성을 가지는 것으로 측정되었다. 본 논문에서 개발한 SSPA는 S-대역을 사용하는 레이더시스템의 송신단에 적용될 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제15권3호
• /
• pp.334-341
• /
• 2015

This research outlines the design of a HR-TDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a $0.18{\mu}m$ CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2S-VTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
• /
• pp.545-548
• /
• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

• 대한전자공학회논문지SD
• /
• 제44권3호
• /
• pp.26-34
• /
• 2007

본 논문에서는 신체 임피던스 측정법(Bioelectrical Impedance Analysis, 이하 BIA)을 기초로 한 체지방 측정 칩 설계에 대한 내용을 서술하였다. 제안된 회로는 인체에 전류 신호를 인가하는 회로, 인체를 통해 나온 전압 신호를 측정하는 회로, 회로의 동작을 제어하는 마이크로 콘트롤러(Micom), 그리고 분석프로그램이 내장된 메모리(SRAM, EEPROMs) 의 모든 기능을 하나의 칩에 집적하였다. 특히 정밀한 인체 임피던스 측정을 위하여 다주파수 동작이 가능한 대역통과필터(Band Pass Filter, BPF)를 설계하였다. 또한, 설계된 대역통과필터는 weak inversion 영역에서 동작하기 때문에 면적과 전력소모를 줄일 수 있었다. 그리고 측정부분 회로의 성능을 개선하기 위해서 차동차이증폭기(Differential difference amplifier, DDA)를 이용한 새로운 전파정류기(Full wave rectifier, FWR)를 설계하였다. 또한 이 회로는 마지막 단에 연결될 아날로그-디지털 변환기(ADC)의 설계에 대한 부담을 덜어주는 장점도 있다. 이 칩의 시제품은 CMOS 0.35um 공정을 이용하였고 전력소모는 모든 주파수에서 6mW 이며 전원전압은 3.3V이다. 전체 칩의 크기는 $5mm\times5mm$ 이다.

• 소음진동
• /
• 제9권5호
• /
• pp.1036-1041
• /
• 1999

This paper aims for the development of the high power sonar system for measuring the velocity of a moving object. The high power sonar system transmits two gated 190 kHz sinusoidal signals with 1.6 [ms] time interval to the moving object. Then the sonar system detects and calculates the changed time delay of the reflected ultrasonic signals in order to derive the velocity of the moving object. The transmission part uses a high power amplifier so that 250 W gated sinusoidal signals can be transmitted to the transmitter. 1M RAM is utilized for transmitting and storing of the ultrasonic signals. The time delay is calculted by the cross-correlation technique between the transmitted signals and the received signals. The measured value from the high power sonar system is compared with directly measured values by photo diodes. The result confirms the adjacency to 0.3% error.