• Title/Summary/Keyword: 2D layer

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Properties of $ Y_2O_3$ Thin Films Prepared by ICBD Method (ICBD 법에 의한 $ Y_2O_3$박막특성에 관한 연구)

  • Jeon, J. S.;Moon, J.;Lee, S. I.;Shim, T. E.;Hwang, J. N.
    • Journal of the Korean Vacuum Society
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    • v.5 no.3
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    • pp.245-250
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    • 1996
  • $Y_2O_3$ thin film on si(100) was successfully grown by ionized cluster beam(ICBD) technique at substrate temperature of around $500^{\circ}C$ and pressure of ~$10^{-5}$Torr.To prevent the oxidation of Si substrae, a very thin yttrium layer was deposited on Si before reactive depositing of oxygen and yttrium source. In asdeposited stage, b.c.c and h.c.p strucutres of $Y_2O_3$ were observed from S-ary analysis. From the observation of spots and ring patterns in selected area diffractin(SAD) patterns. crystallane formation and growth could be proceeded during the deposition. $Y_2O_3$/mixed layer/$SiO_2=170\AA/50\AA/10\AA$ structure were verified by high resolution transmition electron imcroscopy(HRTEM) image, and the formation of amorphous layer of SiO2 was discussed . Electricla charateristics of the film were also investigated . In as-deposited Pt/$Y_2O_3$/Si sturcuture, leakage current was less than $10^{-6}$A/$\textrm{cm}^2$ at 7MV/cm strength.

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Successful Examples of 3D Printing Technology-based Start-up Enterprises (3D 프린팅 기술 기반 창업 성공 사례)

  • Shim, Jin-Hyung;Yun, Won Soo;Ko, Tae Jo
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.15 no.2
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    • pp.104-110
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    • 2016
  • The process of three-dimensional (3D) printing (also known as "rapid prototyping" and "additive manufacturing") uses computer-created digital models to produce 3D objects with a desired shape by stacking materials through a layer-by-layer process. The industrial potential and feasibility of 3D printing technology were recently highlighted in President Obama's State of the Union address in 2013. Since his speech, worldwide investment in and attention toward 3D printing technology have increased explosively. In addition, a number of 3D printing technology-based start-up companies have been established and evaluated as emerging enterprises making successful business models. In this paper, successful start-up companies (domestic and overseas) based on 3D printing technology will be reviewed.

Analysis of Lamb wave propagation on a plate using the spectral element method (스펙트럼 요소법을 이용한 판 구조물의 램파 전달 해석)

  • Lim, Ki-Lyong;Kim, Eun-Jin;Choi, Kwang-Kyu;Park, Hyun-Woo
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2008.11a
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    • pp.71-81
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    • 2008
  • This paper proposes a spectral element which can represent dynamic responses in high frequency domain such as Lamb waves on a thin plate. A two layer beam model under 2-D plane strain condition is introduced to simulate high-frequency dynamic responses induced by piezoelectric layer (PZT layer) bonded on a base plate. In the two layer beam model, a PZT layer is assumed to be rigidly bonded on a base beam. Mindlin-Herrmann and Timoshenko beam theories are employed to represent the first symmetric and anti-symmetric Lamb wave modes on a base plate, respectively. The Bernoulli beam theory and 1-D linear piezoelectricity are used to model the electro-mechanical behavior of a PZT layer. The equations of motions of a two layer beam model are derived through Hamilton's principle. The necessary boundary conditions associated with electro mechanical properties of a PZT layer are formulated in the context of dual functions of a PZT layer as an actuator and a sensor. General spectral shape functions of response field and the associated boundary conditions are formulated through equations of motions converted into frequency domain. A detailed spectrum element formulation for composing the dynamic stiffness matrix of a two layer beam model is presented as well. The validity of the proposed spectral element is demonstrated through comparison results with the conventional 2-D FEM and the previously developed spectral elements.

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Effect of Underlying Layer Modeling on Curling Behavior of Concrete Slabs on Grade under Environmental Loads (하부층 모델링에 따른 지반 위 콘크리트 슬래브의 환경하중 하의 컬링 거동 분석)

  • Kim, Seong-Min;Shim, Jae-Soo;Yoon, Dong-Joo
    • International Journal of Highway Engineering
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    • v.10 no.3
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    • pp.209-220
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    • 2008
  • This paper presents the differences in the analysis results according to the underlying layer modeling methods when analyzing the curling behaviors of the concrete slabs on grade under environmental loads. The models of the slab on grade system considered in this study included a three-dimensional(3D) model, a model composed of 3D slab and springs for underlying layers, and a model composed of 2D slab and springs for underlying layers. First, when the underlying layer consisted of one layer, the curling behaviors according to the different models were compared. Then, the underlying layers that consisted of two different materials and thicknesses were considered. The results of this study showed that the tensionless spring model for the underlying layer gave very accurate results when the underlying layer consisted of one layer. However, when the underlying layers consisted of two layers, the spring model for the underlying layers could overestimate the displacements and underestimate the maximum stress with a large elastic modulus of upper underlying layer, a small elastic modulus of under underlying layer, and thick underlying layers.

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Interface trap density distribution in 3D sequential Integrated-Circuit and Its effect (3차원 순차적 집적회로에서 계면 포획 전하 밀도 분포와 그 영향)

  • Ahn, TaeJun;Lee, Si Hyun;Yu, YunSeop
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.12
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    • pp.2899-2904
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    • 2015
  • This paper introduces about the effect on $I_{DS}-V_{GS}$ characteristic of transistor that interface trap charge is created by damage due to heat in a 3D sequential inverter. A interface trap charge distribution in oxide layer in a 3D sequential inverter is extracted using two-dimensional device simulator. The variation of threshold voltage of top transistor according to the gate voltage variation of bottom transistor is also described in terms of Inter Layer Dielectric (ILD) length of 3D sequential inverter, considering the extracted interface trap charge distribution. The extracted interface trap density distribution shows that the bottom $HfO_2$ layer and both the bottom and top $SiO_2$ layer were relatively more affected by heat than the top $HfO_2$ layer with latest process. The threshold voltage variations of the shorter length of ILD in 3D sequential inverter under 50nm is higher than those over 50nm. The $V_{th}$ variation considering the interface trap charge distribution changes less than that excluding it.

The Design and Performance Analysis of Physical Layer for VDL Mode-2 (VDL Mode-2 물리 계층 설계 및 성능 분석)

  • Choi, Jun-Su;Lee, Han-Seong;Kim, Tae-Sik;Kim, In-Kyu;Kim, Hyoun-Kyoung
    • Journal of Advanced Navigation Technology
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    • v.11 no.1
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    • pp.17-23
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    • 2007
  • This paper, describes the VDR physical layer design in VDL Mode-2 in order to meet the requirements of International standards. VDR's frequency band is 117.975~137MHz, and CSMA(Carrier Sense Multiple Access), D8PSK(Differential Eight Phase Shift Keyed), 25KHz's channel bandwidth use. The analysis of the isolated channel from near channels, sensitivity of the receiver, dynamic range of the receiver, linear of the transmitter and energy of spurious for linear and non-linear simulation as a requirement condition of performance of VDR and teaches the course of design. The transmitting power level should be lower than 5dB from Po1dB point and the selected IF frequency is 45MHz to suppress the spurious signals. The receiver designed has 4.5dB of Noise figure, 27.52dB of Es/No, Mixer isolation up to 30dB, IIP3 power of LNA up to +10dBm to minimize the intermodulation.

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Study on Via hole formation in multi layer MCM-D substrate using photosensitive BCB (감광성 BCB를 사용한 다층 MCM-D 기판에서 비아홀 형성에 관한 연구)

  • 주철원;최효상;안용호;정동철;김정훈;한병성
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.07a
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    • pp.99-102
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    • 2000
  • Via for achieving reliable fabrication of MCM-D substrate was formed on the photosensitive BCB layer. MCM-D substrate consists of photosensitive BCB(Benzocyclobutene) interlayer dielectric and copper conductors. In order to form the vias in photosensitive BCB layer, the process of BCB and plasme etch using $C_2$F$_{6}$ gas were evaluated. The thickness of BCB after soft bake was shrunk down to 60% of the original. AES analysis was done on two vias, one is etched in $C_2$F$_{6}$ gas and the other is non etched. On via etched in $C_2$F$_{6}$, native C was detected and the amount of native C was reduced after Ar sputter. On via non etched in $C_2$F$_{6}$, organic C was detected and amount of organic C was reduced a little after Ar sputter. As a result of AES, BCB residue was not removed by Ar sputter, so plasma etch is necessary for achieving reliable via.ble via.

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The 1/f Noise Analysis of 3D SONOS Multi Layer Flash Memory Devices Fabricated on Nitride or Oxide Layer (산화막과 질화막 위에 제작된 3D SONOS 다층 구조 플래시 메모리소자의 1/f 잡음 특성 분석)

  • Lee, Sang-Youl;Oh, Jae-Sub;Yang, Seung-Dong;Jeong, Kwang-Seok;Yun, Ho-Jin;Kim, Yu-Mi;Lee, Hi-Deok;Lee, Ga-Won
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.25 no.2
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    • pp.85-90
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    • 2012
  • In this paper, we compared and analyzed 3D silicon-oxide-nitride-oxide-silicon (SONOS) multi layer flash memory devices fabricated on nitride or oxide layer, respectively. The device fabricated on nitride layer has inferior electrical properties than that fabricated on oxide layer. However, the device on nitride layer has faster program / erase speed (P/E speed) than that on the oxide layer, although having inferior electrical performance. Afterwards, to find out the reason why the device on nitride has faster P/E speed, 1/f noise analysis of both devices is investigated. From gate bias dependance, both devices follow the mobility fluctuation model which results from the lattice scattering and defects in the channel layer. In addition, the device on nitride with better memory characteristics has higher normalized drain current noise power spectral density ($S_{ID}/I^2_D$>), which means that it has more traps and defects in the channel layer. The apparent hooge's noise parameter (${\alpha}_{app}$) to represent the grain boundary trap density and the height of grain boundary potential barrier is considered. The device on nitride has higher ${\alpha}_{app}$ values, which can be explained due to more grain boundary traps. Therefore, the reason why the devices on nitride and oxide have a different P/E speed can be explained due to the trapping/de-trapping of free carriers into more grain boundary trap sites in channel layer.

2-D Consolidation Numerical Analysis of Multi_Layered Soils (다층 지반의 2차원 압밀 수치해석)

  • 김팔규;류권일;남상규;이재식
    • Proceedings of the Korean Geotechical Society Conference
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    • 2000.03b
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    • pp.467-474
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    • 2000
  • The application of Terzaghi's theory of consolidation for analysing the settlement of multi-layered soils is not strictly valid because the theory involves an assumption that the soil is homogeneous. The settlement of stratified soils with confined aquifer can be analysed using numerical techniques whereby the governing differential equation is replaced by 2-dimensional finite difference approximations. The problems of discontinuous layer interface are very important in the algorithm and programming for the analysis of multi-layered consolidation using a numerical analysis, finite difference method(F.D.M.). Better results can be obtained by the process for discontinuous layer interface, since it can help consolidation analysis to model the actual ground The purpose of this paper provides an efficient computer algorithm based on numerical analysis using finite difference method(F.D.M) which account for multi-layered soils with confined aquifer to determine the degree of consolidation and excess pore pressures relative to time and positions more realistically.

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High Quality Non-Transfer Single-Layer Graphene Process Grown Directly on Ti(10 nm)-Buffered Layer for Photo Lithography Process (포토 리소그래피 공정을 위한 Ti(10 nm)-Buffered층 위에 직접 성장된 고품질 무전사 단층 그래핀 공정)

  • Oh, Keo-Ryong;Han, Yire;Eom, Ji-Ho;Yoon, Soon-Gil
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.34 no.1
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    • pp.21-26
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    • 2021
  • Single-layer graphene is grown directly on Ti-buffered SiO2 at 100℃. As a result of the AFM measurement of the Ti buffer layer, the roughness of approximately 0.2 nm has been improved. Moreover, the Raman measurement of graphene grown on it shows that the D/G intensity ratio is extremely small, approximately 0.01, and there are no defects. In addition, the 2D/G intensity ratio had a value of approximately 2.1 for single-layer graphene. The sheet resistance is also 89 Ω/□, demonstrating excellent characteristics. The problem was solved by using graphene and a lift-off patterning method. Low-temperature direct-grown graphene does not deteriorate after the patterning process and can be used for device and micro-patterning research.